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-rw-r--r--src/include/cpu/cpu.h11
-rw-r--r--src/include/cpu/cpufixup.h24
-rw-r--r--src/include/cpu/k7/cpufixup.h6
-rw-r--r--src/include/cpu/k7/mtrr.h42
-rw-r--r--src/include/cpu/k8/cpufixup.h6
-rw-r--r--src/include/cpu/k8/mtrr.h45
-rw-r--r--src/include/cpu/p5/cpuid.h25
-rw-r--r--src/include/cpu/p6/apic.h175
-rw-r--r--src/include/cpu/p6/cpufixup.h6
-rw-r--r--src/include/cpu/p6/msr.h33
-rw-r--r--src/include/cpu/p6/mtrr.h44
11 files changed, 417 insertions, 0 deletions
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
new file mode 100644
index 0000000000..208dab055b
--- /dev/null
+++ b/src/include/cpu/cpu.h
@@ -0,0 +1,11 @@
+#ifndef CPU_CPU_H
+#define CPU_CPU_H
+
+#include <mem.h>
+
+unsigned long cpu_initialize(struct mem_range *mem);
+#define CPU_ENABLED 1 /* Processor is available */
+#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
+
+
+#endif /* CPU_CPU_H */
diff --git a/src/include/cpu/cpufixup.h b/src/include/cpu/cpufixup.h
new file mode 100644
index 0000000000..b23afa510a
--- /dev/null
+++ b/src/include/cpu/cpufixup.h
@@ -0,0 +1,24 @@
+#ifndef CPU_CPUFIXUP_H
+#define CPU_CPUFIXUP_H
+
+struct mem_range;
+
+#include <cpu/k8/cpufixup.h>
+#include <cpu/k7/cpufixup.h>
+#include <cpu/p6/cpufixup.h>
+
+#if CPU_FIXUP == 1
+# if defined(k8)
+# define cpufixup(mem) k8_cpufixup(mem)
+# elif defined(k7)
+# define cpufixup(mem) k7_cpufixup(mem)
+# elif defined(i786)
+# define cpufixup(mem) i786_cpufixup(mem)
+# elif defined(i686)
+# define cpufixup(mem) p6_cpufixup(mem)
+# endif
+#else
+# define cpufixup(mem) do {} while(0)
+#endif
+
+#endif /* CPU_CPUFIXUP_H */
diff --git a/src/include/cpu/k7/cpufixup.h b/src/include/cpu/k7/cpufixup.h
new file mode 100644
index 0000000000..0e3db3d655
--- /dev/null
+++ b/src/include/cpu/k7/cpufixup.h
@@ -0,0 +1,6 @@
+#ifndef CPU_K7_CPUFIXUP_H
+#define CPU_K7_CPUFIXUP_H
+
+void k7_cpufixup(struct mem_range *mem);
+
+#endif /* CPU_K7_CPUFIXUP_H */
diff --git a/src/include/cpu/k7/mtrr.h b/src/include/cpu/k7/mtrr.h
new file mode 100644
index 0000000000..ea376da2df
--- /dev/null
+++ b/src/include/cpu/k7/mtrr.h
@@ -0,0 +1,42 @@
+#ifndef CPU_K7_MTRR_H
+#define CPU_K7_MTRR_H
+
+#include <cpu/p6/mtrr.h>
+
+#define IORR_FIRST 0xC0010016
+#define IORR_LAST 0xC0010019
+#define SYSCFG 0xC0010010
+
+#define MTRR_READ_MEM (1 << 4)
+#define MTRR_WRITE_MEM (1 << 3)
+
+#define SYSCFG_MSR 0xC0010010
+#define SYSCFG_MSR_EvictEn (1 << 22)
+#define SYSCFG_MSR_TOM2En (1 << 21)
+#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
+#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
+#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
+#define SYSCFG_MSR_UcLockEn (1 << 17)
+#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
+#define SYSCFG_MSR_SysEccEn (1 << 15)
+#define SYSCFG_MSR_RdBlkL2WayEn (1 << 14)
+#define SYSCFG_MSR_SysFillValIsD1 (1 << 13)
+#define SYSCFG_MSR_IcInclusive (1 << 12)
+#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
+#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
+#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
+#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
+#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
+#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
+
+
+
+#define IORR0_BASE 0xC0010016
+#define IORR0_MASK 0xC0010017
+#define IORR1_BASE 0xC0010018
+#define IORR1_MASK 0xC0010019
+#define TOP_MEM 0xC001001A
+#define TOP_MEM2 0xC001001D
+#define HWCR_MSR 0xC0010015
+
+#endif /* CPU_K7_MTRR_H */
diff --git a/src/include/cpu/k8/cpufixup.h b/src/include/cpu/k8/cpufixup.h
new file mode 100644
index 0000000000..9500ec216e
--- /dev/null
+++ b/src/include/cpu/k8/cpufixup.h
@@ -0,0 +1,6 @@
+#ifndef CPU_K8_CPUFIXUP_H
+#define CPU_K8_CPUFIXUP_H
+
+void k8_cpufixup(struct mem_range *mem);
+
+#endif /* CPU_K8_CPUFIXUP_H */
diff --git a/src/include/cpu/k8/mtrr.h b/src/include/cpu/k8/mtrr.h
new file mode 100644
index 0000000000..ce9e6d4d04
--- /dev/null
+++ b/src/include/cpu/k8/mtrr.h
@@ -0,0 +1,45 @@
+#ifndef CPU_K8_MTRR_H
+#define CPU_K8_MTRR_H
+
+#include <cpu/k7/mtrr.h>
+
+#if 0
+#define IORR_FIRST 0xC0010016
+#define IORR_LAST 0xC0010019
+#define SYSCFG 0xC0010010
+
+#define MTRR_READ_MEM (1 << 4)
+#define MTRR_WRITE_MEM (1 << 3)
+
+#define SYSCFG_MSR 0xC0010010
+#define SYSCFG_MSR_EvictEn (1 << 22)
+#define SYSCFG_MSR_TOM2En (1 << 21)
+#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
+#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
+#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
+#define SYSCFG_MSR_UcLockEn (1 << 17)
+#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
+#define SYSCFG_MSR_SysEccEn (1 << 15)
+#define SYSCFG_MSR_RdBlkL2WayEn (1 << 14)
+#define SYSCFG_MSR_SysFillValIsD1 (1 << 13)
+#define SYSCFG_MSR_IcInclusive (1 << 12)
+#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
+#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
+#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
+#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
+#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
+#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
+
+
+
+#define IORR0_BASE 0xC0010016
+#define IORR0_MASK 0xC0010017
+#define IORR1_BASE 0xC0010018
+#define IORR1_MASK 0xC0010019
+#define TOP_MEM 0xC001001A
+#define TOP_MEM2 0xC001001D
+#define HWCR_MSR 0xC0010015
+
+#endif
+
+#endif /* CPU_K8_MTRR_H */
diff --git a/src/include/cpu/p5/cpuid.h b/src/include/cpu/p5/cpuid.h
new file mode 100644
index 0000000000..b8ffc88a84
--- /dev/null
+++ b/src/include/cpu/p5/cpuid.h
@@ -0,0 +1,25 @@
+#ifndef CPU_P5_CPUID_H
+#define CPU_P5_CPUID_H
+
+int mtrr_check(void);
+void display_cpuid(void);
+
+/*
+ * Generic CPUID function. copied from Linux kernel headers
+ */
+
+static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
+{
+ __asm__("pushl %%ebx\n\t"
+ "cpuid\n\t"
+ "movl %%ebx, %%esi\n\t"
+ "popl %%ebx\n\t"
+ : "=a" (*eax),
+ "=S" (*ebx),
+ "=c" (*ecx),
+ "=d" (*edx)
+ : "a" (op)
+ : "cc");
+}
+
+#endif /* CPU_P5_CPUID_H */
diff --git a/src/include/cpu/p6/apic.h b/src/include/cpu/p6/apic.h
new file mode 100644
index 0000000000..b91cdb2a86
--- /dev/null
+++ b/src/include/cpu/p6/apic.h
@@ -0,0 +1,175 @@
+#ifndef APIC_H
+#define APIC_H
+
+#define APIC_BASE_MSR 0x1B
+#define APIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
+#define APIC_BASE_MSR_ENABLE (1 << 11)
+#define APIC_BASE_MSR_ADDR_MASK 0xFFFFF000
+
+#define APIC_DEFAULT_BASE 0xfee00000
+
+#define APIC_ID 0x020
+#define APIC_LVR 0x030
+#define APIC_ARBID 0x090
+#define APIC_RRR 0x0C0
+#define APIC_SVR 0x0f0
+#define APIC_SPIV 0x0f0
+#define APIC_SPIV_ENABLE 0x100
+#define APIC_ESR 0x280
+#define APIC_ESR_SEND_CS 0x00001
+#define APIC_ESR_RECV_CS 0x00002
+#define APIC_ESR_SEND_ACC 0x00004
+#define APIC_ESR_RECV_ACC 0x00008
+#define APIC_ESR_SENDILL 0x00020
+#define APIC_ESR_RECVILL 0x00040
+#define APIC_ESR_ILLREGA 0x00080
+#define APIC_ICR 0x300
+#define APIC_DEST_SELF 0x40000
+#define APIC_DEST_ALLINC 0x80000
+#define APIC_DEST_ALLBUT 0xC0000
+#define APIC_ICR_RR_MASK 0x30000
+#define APIC_ICR_RR_INVALID 0x00000
+#define APIC_ICR_RR_INPROG 0x10000
+#define APIC_ICR_RR_VALID 0x20000
+#define APIC_INT_LEVELTRIG 0x08000
+#define APIC_INT_ASSERT 0x04000
+#define APIC_ICR_BUSY 0x01000
+#define APIC_DEST_LOGICAL 0x00800
+#define APIC_DM_FIXED 0x00000
+#define APIC_DM_LOWEST 0x00100
+#define APIC_DM_SMI 0x00200
+#define APIC_DM_REMRD 0x00300
+#define APIC_DM_NMI 0x00400
+#define APIC_DM_INIT 0x00500
+#define APIC_DM_STARTUP 0x00600
+#define APIC_DM_EXTINT 0x00700
+#define APIC_VECTOR_MASK 0x000FF
+#define APIC_ICR2 0x310
+#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
+#define SET_APIC_DEST_FIELD(x) ((x)<<24)
+#define APIC_LVTT 0x320
+#define APIC_LVTPC 0x340
+#define APIC_LVT0 0x350
+#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
+#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
+#define SET_APIC_TIMER_BASE(x) (((x)<<18))
+#define APIC_TIMER_BASE_CLKIN 0x0
+#define APIC_TIMER_BASE_TMBASE 0x1
+#define APIC_TIMER_BASE_DIV 0x2
+#define APIC_LVT_TIMER_PERIODIC (1<<17)
+#define APIC_LVT_MASKED (1<<16)
+#define APIC_LVT_LEVEL_TRIGGER (1<<15)
+#define APIC_LVT_REMOTE_IRR (1<<14)
+#define APIC_INPUT_POLARITY (1<<13)
+#define APIC_SEND_PENDING (1<<12)
+#define APIC_LVT_RESERVED_1 (1<<11)
+#define APIC_DELIVERY_MODE_MASK (7<<8)
+#define APIC_DELIVERY_MODE_FIXED (0<<8)
+#define APIC_DELIVERY_MODE_NMI (4<<8)
+#define APIC_DELIVERY_MODE_EXTINT (7<<8)
+#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
+#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
+#define APIC_MODE_FIXED 0x0
+#define APIC_MODE_NMI 0x4
+#define APIC_MODE_EXINT 0x7
+#define APIC_LVT1 0x360
+#define APIC_LVTERR 0x370
+
+
+#if !defined(ASSEMBLY)
+
+#include <console/console.h>
+
+
+#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ * but generally the primitive is invalid, *ptr is output argument. --ANK
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__("xchgb %b0,%1"
+ :"=q" (x)
+ :"m" (*__xg(ptr)), "0" (x)
+ :"memory");
+ break;
+ case 2:
+ __asm__ __volatile__("xchgw %w0,%1"
+ :"=r" (x)
+ :"m" (*__xg(ptr)), "0" (x)
+ :"memory");
+ break;
+ case 4:
+ __asm__ __volatile__("xchgl %0,%1"
+ :"=r" (x)
+ :"m" (*__xg(ptr)), "0" (x)
+ :"memory");
+ break;
+ }
+ return x;
+}
+
+
+static inline unsigned long apic_read(unsigned long reg)
+{
+ return *((volatile unsigned long *)(APIC_DEFAULT_BASE+reg));
+}
+
+extern inline void apic_write_atomic(unsigned long reg, unsigned long v)
+{
+ xchg((volatile unsigned long *)(APIC_DEFAULT_BASE+reg), v);
+}
+
+static inline void apic_write(unsigned long reg, unsigned long v)
+{
+ *((volatile unsigned long *)(APIC_DEFAULT_BASE+reg)) = v;
+}
+
+static inline void apic_wait_icr_idle(void)
+{
+ do { } while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
+}
+
+#ifdef CONFIG_X86_GOOD_APIC
+# define FORCE_READ_AROUND_WRITE 0
+# define apic_read_around(x) apic_read(x)
+# define apic_write_around(x,y) apic_write((x),(y))
+#else
+# define FORCE_READ_AROUND_WRITE 1
+# define apic_read_around(x) apic_read(x)
+# define apic_write_around(x,y) apic_write_atomic((x),(y))
+#endif
+
+static inline int apic_remote_read(int apicid, int reg, unsigned long *pvalue)
+{
+ int timeout;
+ unsigned long status;
+ int result;
+ apic_wait_icr_idle();
+ apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
+ apic_write_around(APIC_ICR, APIC_DM_REMRD | (reg >> 4));
+ timeout = 0;
+ do {
+#if 0
+ udelay(100);
+#endif
+ status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
+ } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
+
+ result = -1;
+ if (status == APIC_ICR_RR_VALID) {
+ *pvalue = apic_read(APIC_RRR);
+ result = 0;
+ }
+ return result;
+}
+#endif /* ASSEMBLY */
+
+#endif /* APIC_H */
diff --git a/src/include/cpu/p6/cpufixup.h b/src/include/cpu/p6/cpufixup.h
new file mode 100644
index 0000000000..9b0f2fa096
--- /dev/null
+++ b/src/include/cpu/p6/cpufixup.h
@@ -0,0 +1,6 @@
+#ifndef CPU_P6_CPUFIXUP_H
+#define CPU_P6_CPUFIXUP_H
+
+void p6_cpufixup(struct mem_range *mem);
+
+#endif /* CPU_P6_CPUFIXUP_H */
diff --git a/src/include/cpu/p6/msr.h b/src/include/cpu/p6/msr.h
new file mode 100644
index 0000000000..4977b0201d
--- /dev/null
+++ b/src/include/cpu/p6/msr.h
@@ -0,0 +1,33 @@
+#ifndef CPU_P6_MSR_H
+#define CPU_P6_MSR_H
+
+/*
+ * Access to machine-specific registers (available on 586 and better only)
+ * Note: the rd* operations modify the parameters directly (without using
+ * pointer indirection), this allows gcc to optimize better
+ */
+
+#define rdmsr(msr,val1,val2) \
+ __asm__ __volatile__("rdmsr" \
+ : "=a" (val1), "=d" (val2) \
+ : "c" (msr))
+
+#define wrmsr(msr,val1,val2) \
+ __asm__ __volatile__("wrmsr" \
+ : /* no outputs */ \
+ : "c" (msr), "a" (val1), "d" (val2))
+
+#define rdtsc(low,high) \
+ __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
+
+#define rdtscl(low) \
+ __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
+
+#define rdtscll(val) \
+ __asm__ __volatile__ ("rdtsc" : "=A" (val))
+
+#define rdpmc(counter,low,high) \
+ __asm__ __volatile__("rdpmc" \
+ : "=a" (low), "=d" (high) \
+ : "c" (counter))
+#endif /* CPU_P6_MSR_H */
diff --git a/src/include/cpu/p6/mtrr.h b/src/include/cpu/p6/mtrr.h
new file mode 100644
index 0000000000..16af10b81b
--- /dev/null
+++ b/src/include/cpu/p6/mtrr.h
@@ -0,0 +1,44 @@
+#ifndef __LINUXBIOS_CPU_P6_MTRR_H
+#define __LINUXBIOS_CPU_P6_MTRR_H
+
+/* These are the region types */
+#define MTRR_TYPE_UNCACHABLE 0
+#define MTRR_TYPE_WRCOMB 1
+/*#define MTRR_TYPE_ 2*/
+/*#define MTRR_TYPE_ 3*/
+#define MTRR_TYPE_WRTHROUGH 4
+#define MTRR_TYPE_WRPROT 5
+#define MTRR_TYPE_WRBACK 6
+#define MTRR_NUM_TYPES 7
+
+#define MTRRcap_MSR 0x0fe
+#define MTRRdefType_MSR 0x2ff
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define NUM_FIXED_RANGES 88
+#define MTRRfix64K_00000_MSR 0x250
+#define MTRRfix16K_80000_MSR 0x258
+#define MTRRfix16K_A0000_MSR 0x259
+#define MTRRfix4K_C0000_MSR 0x268
+#define MTRRfix4K_C8000_MSR 0x269
+#define MTRRfix4K_D0000_MSR 0x26a
+#define MTRRfix4K_D8000_MSR 0x26b
+#define MTRRfix4K_E0000_MSR 0x26c
+#define MTRRfix4K_E8000_MSR 0x26d
+#define MTRRfix4K_F0000_MSR 0x26e
+#define MTRRfix4K_F8000_MSR 0x26f
+
+
+#if !defined(ASSEMBLY)
+
+void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type);
+#if defined(INTEL_PPRO_MTRR)
+struct mem_range;
+void setup_mtrrs(struct mem_range *mem);
+#endif
+
+#endif /* ASSEMBLY */
+
+#endif /* __LINUXBIOS_CPU_P6_MTRR_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 10:22:28 +0000