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-rw-r--r--src/include/cpu/x86/msr.h12
-rw-r--r--src/include/cpu/x86/pae.h8
2 files changed, 20 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 8070000322..c2e99446e5 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -1,6 +1,18 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
+/* Intel SDM: Table 2-1
+ * IA-32 architectural MSR: Extended Feature Enable Register
+ */
+#define IA32_EFER 0xC0000080
+#define EFER_NXE (1 << 11)
+#define EFER_LMA (1 << 10)
+#define EFER_LME (1 << 8)
+#define EFER_SCE (1 << 0)
+
+/* Page attribute type MSR */
+#define MSR_IA32_PAT 0x277
+
#if defined(__ROMCC__)
typedef __builtin_msr_t msr_t;
diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h
index eb8fa5a91c..9b9f27b688 100644
--- a/src/include/cpu/x86/pae.h
+++ b/src/include/cpu/x86/pae.h
@@ -1,6 +1,14 @@
#ifndef CPU_X86_PAE_H
#define CPU_X86_PAE_H
+#include <stdint.h>
+
+/* Set/Clear NXE bit in IA32_EFER MSR */
+void paging_set_nxe(int enable);
+
+/* Set PAT MSR */
+void paging_set_pat(uint64_t pat);
+
#define MAPPING_ERROR ((void *)0xffffffffUL)
void *map_2M_page(unsigned long page);