7 files changed, 0 insertions, 9 deletions
diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h
index 8596ce519d..b656a284b3 100644
--- a/src/include/cpu/intel/em64t100_save_state.h
+++ b/src/include/cpu/intel/em64t100_save_state.h
@@ -66,7 +66,6 @@ typedef struct {
 	u64	rsi;
 	u64	rdi;
 
-
 	u64	io_mem_addr;
 	u32	io_misc_info;
 
diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h
index 2e4e0d5748..6884b285b5 100644
--- a/src/include/cpu/intel/em64t101_save_state.h
+++ b/src/include/cpu/intel/em64t101_save_state.h
@@ -6,7 +6,6 @@
 #include <types.h>
 #include <cpu/x86/smm.h>
 
-
 /* Intel Revision 30101 SMM State-Save Area
  * The following processor architectures use this:
  * - Westmere
@@ -83,7 +82,6 @@ typedef struct {
 	u64	rsi;
 	u64	rdi;
 
-
 	u64	io_mem_addr;
 	u32	io_misc_info;
 
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index 07fe0381a1..126aa2a4e2 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_
 
 bool cpu_has_alternative_smrr(void);
 
-
 #define MSR_PRMRR_PHYS_BASE 0x1f4
 #define MSR_PRMRR_PHYS_MASK 0x1f5
 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index d66b8e2a7e..e085e34230 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -18,7 +18,6 @@
  */
 #define PMB1_BASE 0x800
 
-
 /* Speedstep related MSRs */
 #define MSR_THERM2_CTL		0x19D
 #define MSR_EBC_FREQUENCY_ID	0x2c
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 1573eeff7f..3deb133240 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -299,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
 	return MCA_ERRTYPE_UNKNOWN;
 }
 
-
 /* Helper for setting single MSR bits */
 static inline void msr_set_bit(unsigned int reg, unsigned int bit)
 {
@@ -318,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit)
 	wrmsr(reg, msr);
 }
 
-
 #endif /* __ASSEMBLER__ */
 #endif /* CPU_X86_MSR_H */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 6e30199c5f..3bf8301cfd 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -27,7 +27,6 @@
 #define MTRR_DEF_TYPE_EN		(1 << 11)
 #define MTRR_DEF_TYPE_FIX_EN		(1 << 10)
 
-
 #define IA32_SMRR_PHYS_BASE		0x1f2
 #define IA32_SMRR_PHYS_MASK		0x1f3
 #define SMRR_PHYS_MASK_LOCK		(1 << 10)
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index fce39b774d..077f964335 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -3,7 +3,6 @@
 
 #include <console/post_codes.h>
 
-
 #if CONFIG(POST_IO)
 #define post_code(value)        \
 	movb    $value, %al;    \