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-rw-r--r--src/include/spd.h136
1 files changed, 92 insertions, 44 deletions
diff --git a/src/include/spd.h b/src/include/spd.h
index 0bc7898749..9ada5c3c6d 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -34,64 +34,110 @@
#define _SPD_H_
/* Byte numbers. */
-#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */
+/* Number of bytes used by module manufacturer */
+#define SPD_NUM_MANUFACTURER_BYTES 0
#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */
#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */
#define SPD_NUM_ROWS 3 /* Number of row address bits */
-#define SPD_NUM_COLUMNS 4 /* Number of column address bits */
-#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */
+/* Number of column address bits */
+#define SPD_NUM_COLUMNS 4
+/* Number of module rows (banks) */
+#define SPD_NUM_DIMM_BANKS 5
#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */
#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */
-#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */
-#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
+/* Module interface signal levels */
+#define SPD_MODULE_VOLTAGE 8
+/* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
+#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
+/* SDRAM access time from clock (highest CAS latency), CAS access time (Tac,
+ * tCAC)
+ */
+#define SPD_ACCESS_TIME_FROM_CLOCK 10
#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */
#define SPD_REFRESH 12 /* Refresh rate/type */
#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */
-#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */
-#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */
-#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */
-#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */
-#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */
-#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */
-#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */
+/* Error checking SDRAM (data) width */
+#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14
+/* SDRAM device attributes, minimum clock delay for back to back random
+ * column
+ */
+#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15
+/* SDRAM device attributes, burst lengths supported */
+#define SPD_SUPPORTED_BURST_LENGTHS 16
+/* SDRAM device attributes, number of banks on SDRAM device */
+#define SPD_NUM_BANKS_PER_SDRAM 17
+/* SDRAM device attributes, CAS latency */
+#define SPD_ACCEPTABLE_CAS_LATENCIES 18
+/* SDRAM device attributes, CS latency */
+#define SPD_CS_LATENCY 19
+/* SDRAM device attributes, WE latency */
+#define SPD_WE_LATENCY 20
#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */
-#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */
-#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */
-#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */
-#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */
-#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */
-#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */
-#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */
-#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */
-#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */
-#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */
-#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */
-#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */
-#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */
+/* SDRAM device attributes, general */
+#define SPD_DEVICE_ATTRIBUTES_GENERAL 22
+/* SDRAM cycle time (2nd highest CAS latency) */
+#define SPD_SDRAM_CYCLE_TIME_2ND 23
+/* SDRAM access from clock (2nd highest CAS latency) */
+#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24
+/* SDRAM cycle time (3rd highest CAS latency) */
+#define SPD_SDRAM_CYCLE_TIME_3RD 25
+/* SDRAM access from clock (3rd highest CAS latency) */
+#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26
+/* Minimum row precharge time (Trp) */
+#define SPD_MIN_ROW_PRECHARGE_TIME 27
+/* Minimum row active to row active (Trrd) */
+#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28
+/* Minimum RAS to CAS delay (Trcd) */
+#define SPD_MIN_RAS_TO_CAS_DELAY 29
+/* Minimum RAS pulse width (Tras) */
+#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30
+/* Density of each row on module */
+#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31
+/* Command and address signal input setup time */
+#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32
+/* Command and address signal input hold time */
+#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33
+/* Data signal input setup time */
+#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34
#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */
-#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */
-#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */
-#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */
-#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
-#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */
-#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */
-#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */
-#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */
-#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */
+/* Internal write to read command delay (tWTR) */
+#define SPD_INT_WRITE_TO_READ_DELAY 37
+/* Internal read to precharge command delay (tRTP) */
+#define SPD_INT_READ_TO_PRECHARGE_DELAY 38
+/* Memory analysis probe characteristics */
+#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39
+/* Extension of byte 41 (tRC) and byte 42 (tRFC) */
+#define SPD_BYTE_41_42_EXTENSION 40
+/* Minimum active to active auto refresh (tRCmin) */
+#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41
+/* Minimum auto refresh to active/auto refresh (tRFC) */
+#define SPD_MIN_AUTO_REFRESH_TO_ACT 42
+/* Maximum device cycle time (tCKmax) */
+#define SPD_MAX_DEVICE_CYCLE_TIME 43
+/* Maximum skew between DQS and DQ (tDQSQ) */
+#define SPD_MAX_DQS_DQ_SKEW 44
+/* Maximum read data-hold skew factor (tQHS) */
+#define SPD_MAX_READ_DATAHOLD_SKEW 45
#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */
#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
-#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
+/* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
+#define SPD_MANUFACTURER_JEDEC_ID_CODE 64
#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */
-#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
+/* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
+#define SPD_MANUFACTURER_PART_NUMBER 73
#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */
-#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */
-#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */
-#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */
-#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */
-#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
+/* Manufacturing date (byte 93: year, byte 94: week) */
+#define SPD_MANUFACTURING_DATE 93
+/* Assembly serial number (bytes 95-98) */
+#define SPD_ASSEMBLY_SERIAL_NUMBER 95
+/* Manufacturer specific data (bytes 99-125) */
+#define SPD_MANUFACTURER_SPECIFIC_DATA 99
+/* Intel specification for frequency */
+#define SPD_INTEL_SPEC_FOR_FREQUENCY 126
+/* Intel specification details for 100MHz support */
+#define SPD_INTEL_SPEC_100_MHZ 127
/* DRAM specifications use the following naming conventions for SPD locations */
#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME
@@ -100,8 +146,10 @@
#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE
#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME
-#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
-#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+/* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
+#define SPD_tRC 41
+/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+#define SPD_tRFC 42
/* SPD_MEMORY_TYPE values. */