diff options
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/amd/microcode.h | 3 | ||||
| -rw-r--r-- | src/include/cpu/amd/model_fxx_rev.h | 42 | ||||
| -rw-r--r-- | src/include/cpu/x86/mem.h | 2 | ||||
| -rw-r--r-- | src/include/device/device.h | 6 | ||||
| -rw-r--r-- | src/include/device/hypertransport_def.h | 5 | ||||
| -rw-r--r-- | src/include/device/pci.h | 12 | ||||
| -rw-r--r-- | src/include/device/pci_def.h | 1 |
7 files changed, 60 insertions, 11 deletions
diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index 9621090ff2..0ebdeb95ff 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -2,4 +2,5 @@ #define CPU_AMD_MICORCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); -#endif /* CPU_AMD_MICROCODE_H */
\ No newline at end of file +#endif /* CPU_AMD_MICROCODE_H */ + diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 4c2a7ce940..ca6d69d7a0 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -1,5 +1,6 @@ #include <arch/cpu.h> +#if K8_REV_F_SUPPORT == 0 static inline int is_cpu_rev_a0(void) { return (cpuid_eax(1) & 0xfffef) == 0x0f00; @@ -74,5 +75,46 @@ static int is_e0_later_in_bsp(int nodeid) int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c #endif +#endif + +#if K8_REV_F_SUPPORT == 1 +//AMD_F0_SUPPORT +static inline int is_cpu_pre_f0(void) +{ + return (cpuid_eax(1) & 0xfff0f) < 0x40f00; +} + +static inline int is_cpu_f0(void) +{ + return (cpuid_eax(1) & 0xfff00) == 0x40f00; +} + +static inline int is_cpu_pre_f2(void) +{ + return (cpuid_eax(1) & 0xfff0f) < 0x40f02; +} +#ifdef __ROMCC__ +//AMD_F0_SUPPORT +static int is_cpu_f0_in_bsp(int nodeid) +{ + uint32_t dword; + device_t dev; + dev = PCI_DEV(0, 0x18+nodeid, 3); + dword = pci_read_config32(dev, 0xfc); + return (dword & 0xfff00) == 0x40f00; +} +static int is_cpu_pre_f2_in_bsp(int nodeid) +{ + uint32_t dword; + device_t dev; + dev = PCI_DEV(0, 0x18+nodeid, 3); + dword = pci_read_config32(dev, 0xfc); + return (dword & 0xfff0f) < 0x40f02; +} +#else +int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c +#endif + +#endif diff --git a/src/include/cpu/x86/mem.h b/src/include/cpu/x86/mem.h index 532fc79e0a..530c653277 100644 --- a/src/include/cpu/x86/mem.h +++ b/src/include/cpu/x86/mem.h @@ -6,7 +6,7 @@ static inline void clear_memory(void *addr, unsigned long size) { asm volatile( "cld \n\t" - "rep stosl\n\t" + "rep; stosl\n\t" : /* No outputs */ : "a" (0), "D" (addr), "c" (size>>2) ); diff --git a/src/include/device/device.h b/src/include/device/device.h index aff5616a88..b922e2687e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -48,14 +48,14 @@ struct bus { device_t children; /* devices behind this bridge */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link; /* The index of this link */ - unsigned char secondary; /* secondary bus number */ - unsigned char subordinate; /* max subordinate bus number */ + uint16_t secondary; /* secondary bus number */ + uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; }; -#define MAX_RESOURCES 12 +#define MAX_RESOURCES 12 #define MAX_LINKS 8 /* * There is one device structure for each slot-number/function-number diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index 0b44109f9f..6c12dcf39f 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -11,6 +11,11 @@ #define HT_FREQ_1200Mhz 7 #define HT_FREQ_1400Mhz 8 #define HT_FREQ_1600Mhz 9 +#define HT_FREQ_1800Mhz 10 +#define HT_FREQ_2000Mhz 11 +#define HT_FREQ_2200Mhz 12 +#define HT_FREQ_2400Mhz 13 +#define HT_FREQ_2600Mhz 14 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ #endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 2daa1ca03e..decc20d29b 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -29,12 +29,12 @@ struct pci_operations { /* Common pci bus operations */ struct pci_bus_operations { - uint8_t (*read8) (struct bus *pbus, unsigned char bus, int devfn, int where); - uint16_t (*read16) (struct bus *pbus, unsigned char bus, int devfn, int where); - uint32_t (*read32) (struct bus *pbus, unsigned char bus, int devfn, int where); - void (*write8) (struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t val); - void (*write16) (struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t val); - void (*write32) (struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t val); + uint8_t (*read8) (struct bus *pbus, int bus, int devfn, int where); + uint16_t (*read16) (struct bus *pbus, int bus, int devfn, int where); + uint32_t (*read32) (struct bus *pbus, int bus, int devfn, int where); + void (*write8) (struct bus *pbus, int bus, int devfn, int where, uint8_t val); + void (*write16) (struct bus *pbus, int bus, int devfn, int where, uint16_t val); + void (*write32) (struct bus *pbus, int bus, int devfn, int where, uint32_t val); }; struct pci_driver { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 6fb7ebd385..1e27647d4b 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -201,6 +201,7 @@ #define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */ #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */ #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */ +#define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */ /* Power Management Registers */ |