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Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/elog.h | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/src/include/elog.h b/src/include/elog.h new file mode 100644 index 0000000000..c6599a249c --- /dev/null +++ b/src/include/elog.h @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef ELOG_H_ +#define ELOG_H_ + +#if CONFIG_ELOG + +/* SMI command code for GSMI event logging */ +#define ELOG_GSMI_APM_CNT 0xEF + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +struct elog_event_data_wake { + u8 source; + u32 instance; +} __attribute__ ((packed)); + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 + +extern int elog_init(void); +extern int elog_clear(void); +extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size); +extern void elog_add_event(u8 event_type); +extern void elog_add_event_byte(u8 event_type, u8 data); +extern void elog_add_event_word(u8 event_type, u16 data); +extern void elog_add_event_dword(u8 event_type, u32 data); +extern void elog_add_event_wake(u8 source, u32 instance); + +#endif /* !CONFIG_ELOG */ + +#endif /* ELOG_H_ */ |