diff options
Diffstat (limited to 'src/mainboard/51nb/x210/devicetree.cb')
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 167 |
1 files changed, 167 insertions, 0 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb new file mode 100644 index 0000000000..7ee3b2c87e --- /dev/null +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -0,0 +1,167 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "1" + register "deep_s3_enable_dc" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + register "PmConfigPciClockRun" = "1" + + # Enable Root Ports 3, 4 and 9 + register "PcieRpEnable[2]" = "1" # Ethernet controller + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "0" + register "PcieRpClkSrcNumber[2]" = "0" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + + register "PcieRpEnable[3]" = "1" # Wireless controller + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + + register "PcieRpEnable[8]" = "1" # NVMe controller + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/51nb/npce985la0dx + device pnp 0c09.0 on end + device pnp 4e.5 on end + device pnp 4e.6 on end + device pnp 4e.11 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end |