diff options
Diffstat (limited to 'src/mainboard/Iwill/DK8X/auto.c')
| -rw-r--r-- | src/mainboard/Iwill/DK8X/auto.c | 138 |
1 files changed, 62 insertions, 76 deletions
diff --git a/src/mainboard/Iwill/DK8X/auto.c b/src/mainboard/Iwill/DK8X/auto.c index 9889f23229..b8ca3c82ba 100644 --- a/src/mainboard/Iwill/DK8X/auto.c +++ b/src/mainboard/Iwill/DK8X/auto.c @@ -1,25 +1,51 @@ #define ASSEMBLY 1 #include <stdint.h> #include <device/pci_def.h> -#include <cpu/p6/apic.h> #include <arch/io.h> -#include <device/pnp.h> +#include <device/pnp_def.h> #include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/early_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/k8/apic_timer.c" +#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#include "cpu/p6/boot_cpu.c" +#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/NSC/pc87360/pc87360_early_serial.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" -#define SIO_BASE 0x2e +#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +static void hard_reset(void) +{ + set_bios_reset(); + + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); +} + +/* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ static void memreset_setup(void) { if (is_cpu_pre_c0()) { @@ -103,68 +129,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "sdram/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" -static void enable_lapic(void) -{ - - msr_t msr; - msr = rdmsr(0x1b); - msr.hi &= 0xffffff00; - msr.lo &= 0x000007ff; - msr.lo |= APIC_DEFAULT_BASE | (1 << 11); - wrmsr(0x1b, msr); -} - -static void stop_this_cpu(void) -{ - unsigned apicid; - apicid = apic_read(APIC_ID) >> 24; - - /* Send an APIC INIT to myself */ - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); - /* Wait for the ipi send to finish */ - apic_wait_icr_idle(); - - /* Deassert the APIC INIT */ - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); - /* Wait for the ipi send to finish */ - apic_wait_icr_idle(); - - /* If I haven't halted spin forever */ - for(;;) { - hlt(); - } -} - -#define PC87360_FDC 0x00 -#define PC87360_PP 0x01 -#define PC87360_SP2 0x02 -#define PC87360_SP1 0x03 -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 -#define PC87360_KBCK 0x06 -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -static void pc87360_enable_serial(void) -{ - pnp_set_logical_device(SIO_BASE, PC87360_SP1); - pnp_set_enable(SIO_BASE, 1); - pnp_set_iobase0(SIO_BASE, 0x3f8); -} - #define FIRST_CPU 1 #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -static void main(void) +static void main(unsigned long bist) { - /* - * GPIO28 of 8111 will control H0_MEMRESET_L - * GPIO29 of 8111 will control H1_MEMRESET_L - */ static const struct mem_controller cpu[] = { #if FIRST_CPU { @@ -189,22 +158,38 @@ static void main(void) }, #endif }; - if (cpu_init_detected()) { - asm("jmp __cpu_reset"); - } - enable_lapic(); - init_timer(); - if (!boot_cpu()) { - stop_this_cpu(); + + int needs_reset; + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + amd_early_mtrr_init(); + enable_lapic(); + init_timer(); + /* Has this cpu already booted? */ + if (cpu_init_detected()) { + asm volatile ("jmp __cpu_reset"); + } + distinguish_cpu_resets(); + if (!boot_cpu()) { + stop_this_cpu(); + } } - pc87360_enable_serial(); + /* Setup the console */ + pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); - + needs_reset = setup_coherent_ht_domain(); + needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + #if 0 print_pci_devices(); #endif @@ -212,6 +197,7 @@ static void main(void) #if 0 dump_spd_registers(&cpu[0]); #endif + memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); |