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-rw-r--r--src/mainboard/advansus/a785e-i/Makefile.inc3
-rw-r--r--src/mainboard/advansus/a785e-i/romstage.c7
2 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index d69a9bf869..d7290afedd 100644
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -1,5 +1,4 @@
-#romstage-y += reset.c #FIXME romstage have include test_rest.c
-
+romstage-y += reset.c
ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index ae283a4a3d..1a4a27635b 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -72,14 +72,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "spd.h"
-
#include <reset.h>
-void soft_reset(void)
-{
- set_bios_reset();
- /* link reset */
- outb(0x06, 0x0cf9);
-}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{