diff options
Diffstat (limited to 'src/mainboard/agami/aruma/Options.lb')
| -rw-r--r-- | src/mainboard/agami/aruma/Options.lb | 295 |
1 files changed, 0 insertions, 295 deletions
diff --git a/src/mainboard/agami/aruma/Options.lb b/src/mainboard/agami/aruma/Options.lb deleted file mode 100644 index a6775ea056..0000000000 --- a/src/mainboard/agami/aruma/Options.lb +++ /dev/null @@ -1,295 +0,0 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses CC -uses HOSTCC -uses CROSS_COMPILE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CHIP_NAME - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - - -uses SERIAL_CPU_INIT - -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID - -uses HW_MEM_HOLE_SIZEK -uses CONFIG_PCI_64BIT_PREF_MEM - - -### -### Build options -### - -## -## ROM_SIZE is the size of boot ROM that this board will use. -## -default ROM_SIZE=524288 - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -#default FALLBACK_SIZE=131072 -# 256k -default FALLBACK_SIZE=0x40000 - - -## -## Set this. -## - -default CONFIG_CHIP_NAME=1 - - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Use hard_reset for rebooting, it uses reg. 0xcf9 in the amd8111. -## -default HAVE_HARD_RESET=1 - -## -## set memory hole size -## -default HW_MEM_HOLE_SIZEK=0x300000 -#default HW_MEM_HOLE_SIZEK=0x200000 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=23 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 -default HAVE_ACPI_TABLES=1 - -## extra SSDT num -default ACPI_SSDTX_NUM=3 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=8 -default CONFIG_MAX_PHYSICAL_CPUS=4 -default CONFIG_LOGICAL_CPUS=1 -#default ALLOW_HT_OVERCLOCKING=1 - -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 # SDE was 0 - -#HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0xa - -#real SB Unit ID -#default HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0 -#default SB_HT_CHAIN_ON_BUS0=1 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x4000 -default CONFIG_USE_INIT=0 -#default CONFIG_USE_INIT=1 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="ARUMA" -default MAINBOARD_VENDOR="AGAMI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0 - - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a 32K heap -## -default HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default _RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -#default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - - -## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -#VGA -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -#default CONFIG_CONSOLE_VGA=0 -#default CONFIG_PCI_ROM_RUN=0 - -### End Options.lb -end |