summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/db-ft3b-lc/mainboard.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/amd/db-ft3b-lc/mainboard.c')
-rw-r--r--src/mainboard/amd/db-ft3b-lc/mainboard.c124
1 files changed, 0 insertions, 124 deletions
diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c
deleted file mode 100644
index a3396593f4..0000000000
--- a/src/mainboard/amd/db-ft3b-lc/mainboard.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00730F01/pci_devs.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables. TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
- [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
- /* INTA# - INTH# */
- [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
- /* Misc-nil,0,1,2, INT from Serial irq */
- [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
- [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
- /* IMC INT0 - 5 */
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
- /* USB Devs 18/19/22 INTA-C */
- [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
- /* SATA */
- [0x41] = 0x0F,
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
- [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
- /* INTA# - INTH# */
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- /* Misc-nil,0,1,2, INT from Serial irq */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
- /* IMC INT0 - 5 */
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
- /* USB Devs 18/19/20/22 INTA-C */
- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
- /* SATA */
- [0x41] = 0x13,
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device. Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01. This index will define
- * the interrupt that it should use. Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
- /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
- {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
- {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
- {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
- {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
- {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
- {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
- {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
- {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
- {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
- {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
- {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
- {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
- {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
- {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
- {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
- {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
- pirq_data_ptr = mainboard_pirq_data;
- pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
- intr_data_ptr = mainboard_intr_data;
- picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * enable the dedicated function in mainboard.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};