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-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6d1e4ea31f..534a8e5d49 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {