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-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c16
1 files changed, 4 insertions, 12 deletions
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index c98ae25bc0..ff2c4c411d 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -35,9 +36,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -88,20 +86,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}