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Diffstat (limited to 'src/mainboard/amd/persimmon/romstage.c')
| -rw-r--r-- | src/mainboard/amd/persimmon/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 606780355b..0eb7490c6a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -45,7 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - u8 reg8; // all cores: allow caching of flash chip code and data // (there are no cache-as-ram reliability concerns with family 14h) |