diff options
Diffstat (limited to 'src/mainboard/amd/pistachio/Config.lb')
| -rw-r--r-- | src/mainboard/amd/pistachio/Config.lb | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index 186a60970e..c1f513609e 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -83,8 +83,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## |