diff options
Diffstat (limited to 'src/mainboard/amd/quartet/Config.lb')
| -rw-r--r-- | src/mainboard/amd/quartet/Config.lb | 180 |
1 files changed, 22 insertions, 158 deletions
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb index bd7e11ceb0..c9a1d4203e 100644 --- a/src/mainboard/amd/quartet/Config.lb +++ b/src/mainboard/amd/quartet/Config.lb @@ -1,123 +1,3 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_STREAM -uses CONFIG_ROM_STREAM_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR - - -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=524288 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=1 - -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default LinuxBIOS cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="QUARTET" -default MAINBOARD_VENDOR="AMD" - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE - ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. @@ -136,7 +16,6 @@ end ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_STREAM = 1 ## ## Compute where this copy of linuxBIOS will start in the boot rom @@ -153,12 +32,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end -#cpu k8 end +arch i386 end ## ## Build the objects we have code for in this directory. @@ -182,7 +56,7 @@ makerule ./failover.inc end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h" + depends "$(MAINBOARD)/auto.c option_table.h" action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end makerule ./auto.inc @@ -193,21 +67,20 @@ end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -mainboardinit cpu/i386/bist32.inc -ldscript /cpu/i386/entry16.lds -ldscript /cpu/i386/entry32.lds +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end ### Should this be in the northbridge code? @@ -219,11 +92,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -## -## Setup our mtrrs -## -mainboardinit cpu/k8/earlymtrr.inc - ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should @@ -241,9 +109,12 @@ end ## ## Setup RAM ## -mainboardinit cpu/k8/enable_mmx_sse.inc +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc -mainboardinit cpu/k8/disable_mmx_sse.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc ## ## Include the secondary Configuration files @@ -255,9 +126,9 @@ chip northbridge/amd/amdk8 # mc0 device pci_domain 0 on device pci 18.0 on end device pci 18.0 on end - device pci 18.0 - chip southbridge amd/amd8111 - device pci 0:0.0 on + device pci 18.0 on + chip southbridge/amd/amd8111 + device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 on end @@ -300,8 +171,8 @@ chip northbridge/amd/amdk8 # mc0 device pci 1.3 on end device pci 1.5 on end device pci 1.6 on end - end - end + end # 8111 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -309,13 +180,13 @@ chip northbridge/amd/amdk8 # mc0 chip northbridge/amd/amdk8 # mc1 device pci 19.0 on end device pci 19.0 on - chip southbridge amd/amd8131 # amd8131_0 + chip southbridge/amd/amd8131 # amd8131_0 device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end - chip southbridge amd/amd8131 # amd8131_1 + chip southbridge/amd/amd8131 # amd8131_1 device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end @@ -362,10 +233,3 @@ chip northbridge/amd/amdk8 # mc0 end end -## -## Include the old serial code for those few places that still need it. -## -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -mainboardinit cpu/i386/bist32_fail.inc - |