diff options
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah/Config.lb')
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/Config.lb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb index f54c423fbd..6948a70948 100644 --- a/src/mainboard/amd/serengeti_cheetah/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -17,18 +17,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -154,7 +154,7 @@ else end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT @@ -181,7 +181,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -215,7 +215,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### |