diff options
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c')
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c index 95a3395abe..fb1be8dd28 100644 --- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -45,7 +45,7 @@ static void post_code(uint8_t value) { #endif } #endif -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -59,7 +59,7 @@ static void post_code(uint8_t value) { #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -156,7 +156,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -201,7 +201,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -215,21 +215,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -253,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -265,11 +265,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -284,7 +284,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 |