diff options
Diffstat (limited to 'src/mainboard/amd/thatcher/OemCustomize.c')
| -rw-r--r-- | src/mainboard/amd/thatcher/OemCustomize.c | 42 |
1 files changed, 35 insertions, 7 deletions
diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index c035722c58..a6c98b9026 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 4, PCI Device Number 4, LAN */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) }, }; |