diff options
Diffstat (limited to 'src/mainboard/amd/tilapia_fam10/resourcemap.c')
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/resourcemap.c | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index 37b6d20797..d51e12819e 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -48,13 +48,13 @@ void setup_mb_resource_map(void) * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ void setup_mb_resource_map(void) * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ void setup_mb_resource_map(void) * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ void setup_mb_resource_map(void) * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ void setup_mb_resource_map(void) * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; |