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path: root/src/mainboard/amd/torpedo/BiosCallOuts.c
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Diffstat (limited to 'src/mainboard/amd/torpedo/BiosCallOuts.c')
-rw-r--r--src/mainboard/amd/torpedo/BiosCallOuts.c264
1 files changed, 132 insertions, 132 deletions
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index b64cef37c0..0035a27168 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -43,147 +43,147 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/* Call the host environment interface to provide a user hook opportunity. */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- MEM_DATA_STRUCT *MemData;
- UINT32 AcpiMmioAddr;
- UINT32 GpioMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ MEM_DATA_STRUCT *MemData;
+ UINT32 AcpiMmioAddr;
+ UINT32 GpioMmioAddr;
+ UINT8 Data8;
+ UINT16 Data16;
- FcnData = Data;
- MemData = ConfigPtr;
+ FcnData = Data;
+ MemData = ConfigPtr;
- Status = AGESA_SUCCESS;
- /* Get SB MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ Status = AGESA_SUCCESS;
+ /* Get SB MMIO Base (AcpiMmioAddr) */
+ WriteIo8 (0xCD6, 0x27);
+ Data8 = ReadIo8(0xCD7);
+ Data16 = Data8 << 8;
+ WriteIo8 (0xCD6, 0x26);
+ Data8 = ReadIo8(0xCD7);
+ Data16 |= Data8;
+ AcpiMmioAddr = (UINT32)Data16 << 16;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch(MemData->ParameterListPtr->DDR3Voltage){
- case VOLT1_35:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_25:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_5:
- default:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- }
- return Status;
+ switch(MemData->ParameterListPtr->DDR3Voltage){
+ case VOLT1_35:
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+ Data8 |= (UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ break;
+ case VOLT1_25:
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ break;
+ case VOLT1_5:
+ default:
+ Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+ Data8 |= (UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ }
+ return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- PCIe_SLOT_RESET_INFO *ResetInfo;
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ PCIe_SLOT_RESET_INFO *ResetInfo;
- UINT32 GpioMmioAddr;
- UINT32 AcpiMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
+ UINT32 GpioMmioAddr;
+ UINT32 AcpiMmioAddr;
+ UINT8 Data8;
+ UINT16 Data16;
- FcnData = Data;
- ResetInfo = ConfigPtr;
- // Get SB MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ FcnData = Data;
+ ResetInfo = ConfigPtr;
+ // Get SB MMIO Base (AcpiMmioAddr)
+ WriteIo8(0xCD6, 0x27);
+ Data8 = ReadIo8(0xCD7);
+ Data16 = Data8 << 8;
+ WriteIo8(0xCD6, 0x26);
+ Data8 = ReadIo8(0xCD7);
+ Data16 |= Data8;
+ AcpiMmioAddr = (UINT32)Data16 << 16;
+ Status = AGESA_UNSUPPORTED;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- if (ResetInfo->ResetControl == DeassertSlotReset) {
- if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
- // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
- if (Data8 & BIT7) {
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
- while (!(Data8 & BIT7)) {
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
- }
- // GPIO44: PE_GPIO0 MXM Reset
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
- Status = AGESA_SUCCESS;
- }
- } else {
- Status = AGESA_UNSUPPORTED;
- }
- // Travis
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
- //DE-Assert ALL PCIE RESET
- // APU GPP0 (Dev 4)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
- // APU GPP1 (Dev 5)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
- // APU GPP2 (Dev 6)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
- // APU GPP3 (Dev 7)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
- } else {
- if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
- // GPIO44: PE_GPIO0 MXM Reset
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
- Status = AGESA_SUCCESS;
- }
- // Travis
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
- Data8 &= ~(UINT8)BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
- //Assert ALL PCIE RESET
- // APU GPP0 (Dev 4)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
- // APU GPP1 (Dev 5)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
- // APU GPP2 (Dev 6)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
- // APU GPP3 (Dev 7)
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
- }
- return Status;
+ if (ResetInfo->ResetControl == DeassertSlotReset) {
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
+ // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
+ if (Data8 & BIT7) {
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
+ while (!(Data8 & BIT7)) {
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
+ }
+ // GPIO44: PE_GPIO0 MXM Reset
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
+ Status = AGESA_SUCCESS;
+ }
+ } else {
+ Status = AGESA_UNSUPPORTED;
+ }
+ // Travis
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
+ //DE-Assert ALL PCIE RESET
+ // APU GPP0 (Dev 4)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
+ // APU GPP1 (Dev 5)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
+ // APU GPP2 (Dev 6)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
+ // APU GPP3 (Dev 7)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
+ Data8 |= BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
+ } else {
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
+ // GPIO44: PE_GPIO0 MXM Reset
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
+ Status = AGESA_SUCCESS;
+ }
+ // Travis
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
+ //Assert ALL PCIE RESET
+ // APU GPP0 (Dev 4)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
+ // APU GPP1 (Dev 5)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
+ // APU GPP2 (Dev 6)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
+ // APU GPP3 (Dev 7)
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
+ }
+ return Status;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 17:25:47 +0000