1 files changed, 0 insertions, 131 deletions
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
deleted file mode 100644
index 1ad6cde9db..0000000000
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, BIT2)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, BIT3)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}