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-rw-r--r--src/mainboard/amd/bimini_fam10/Makefile.inc16
-rw-r--r--src/mainboard/amd/bimini_fam10/resourcemap.c6
-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/mahogany_fam10/Makefile.inc16
-rw-r--r--src/mainboard/amd/mahogany_fam10/resourcemap.c6
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc4
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c6
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/tilapia_fam10/Makefile.inc16
-rw-r--r--src/mainboard/amd/tilapia_fam10/resourcemap.c6
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c1
12 files changed, 72 insertions, 8 deletions
diff --git a/src/mainboard/amd/bimini_fam10/Makefile.inc b/src/mainboard/amd/bimini_fam10/Makefile.inc
new file mode 100644
index 0000000000..91d4b39c32
--- /dev/null
+++ b/src/mainboard/amd/bimini_fam10/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += resourcemap.c
+
+ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c
index b647f48129..ce4351f8eb 100644
--- a/src/mainboard/amd/bimini_fam10/resourcemap.c
+++ b/src/mainboard/amd/bimini_fam10/resourcemap.c
@@ -13,7 +13,11 @@
* GNU General Public License for more details.
*/
-static void setup_mb_resource_map(void)
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
+void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 6c40f6e036..3d86b60afc 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -45,7 +45,6 @@
#include "southbridge/amd/sb800/early_setup.c"
#include <spd.h>
-#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
void activate_spd_rom(const struct mem_controller *ctrl);
diff --git a/src/mainboard/amd/mahogany_fam10/Makefile.inc b/src/mainboard/amd/mahogany_fam10/Makefile.inc
new file mode 100644
index 0000000000..91d4b39c32
--- /dev/null
+++ b/src/mainboard/amd/mahogany_fam10/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += resourcemap.c
+
+ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c
index acdf645a54..a4a1d9251a 100644
--- a/src/mainboard/amd/mahogany_fam10/resourcemap.c
+++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c
@@ -15,7 +15,11 @@
-static void setup_mb_resource_map(void)
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
+void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index ef7afdeb71..b0d23b2dec 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -51,7 +51,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
-#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
void activate_spd_rom(const struct mem_controller *ctrl);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
index e826e8153a..c9a38fab7e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
@@ -2,3 +2,7 @@ $(eval $(call asl_template,ssdt2))
$(eval $(call asl_template,ssdt3))
$(eval $(call asl_template,ssdt4))
$(eval $(call asl_template,ssdt5))
+
+romstage-y += resourcemap.c
+
+ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
index 0e47c52784..2a2380a3f9 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
@@ -13,7 +13,11 @@
* GNU General Public License for more details.
*/
-static void setup_mb_resource_map(void)
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
+void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index fcb10b1daa..03d3484105 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -44,7 +44,6 @@
#include "southbridge/amd/amd8111/early_smbus.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
-#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/amd/tilapia_fam10/Makefile.inc b/src/mainboard/amd/tilapia_fam10/Makefile.inc
new file mode 100644
index 0000000000..91d4b39c32
--- /dev/null
+++ b/src/mainboard/amd/tilapia_fam10/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += resourcemap.c
+
+ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c
index 5a4381424a..37b6d20797 100644
--- a/src/mainboard/amd/tilapia_fam10/resourcemap.c
+++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c
@@ -13,7 +13,11 @@
* GNU General Public License for more details.
*/
-static void setup_mb_resource_map(void)
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
+void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 0001f93260..50c7a002dd 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -47,7 +47,6 @@
#include <spd.h>
#include <southbridge/amd/rs780/rs780.h>
-#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 14:02:39 +0000