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-rw-r--r--src/mainboard/amd/bettong/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/bettong/dsdt.asl2
-rw-r--r--src/mainboard/amd/bimini_fam10/devicetree.cb4
-rw-r--r--src/mainboard/amd/bimini_fam10/dsdt.asl38
-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c2
-rw-r--r--src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/db-ft3b-lc/dsdt.asl2
-rw-r--r--src/mainboard/amd/gardenia/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/inagua/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/inagua/acpi/sleep.asl2
-rw-r--r--src/mainboard/amd/inagua/acpi/usb_oc.asl2
-rw-r--r--src/mainboard/amd/lamar/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/lamar/acpi/sleep.asl2
-rw-r--r--src/mainboard/amd/mahogany_fam10/devicetree.cb4
-rw-r--r--src/mainboard/amd/mahogany_fam10/dsdt.asl38
-rw-r--r--src/mainboard/amd/olivehill/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/olivehill/dsdt.asl2
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/olivehillplus/dsdt.asl2
-rw-r--r--src/mainboard/amd/parmer/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/parmer/acpi/sleep.asl2
-rw-r--r--src/mainboard/amd/persimmon/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/persimmon/acpi/sleep.asl2
-rw-r--r--src/mainboard/amd/thatcher/acpi/gpe.asl2
-rw-r--r--src/mainboard/amd/thatcher/acpi/sleep.asl2
-rw-r--r--src/mainboard/amd/tilapia_fam10/devicetree.cb4
-rw-r--r--src/mainboard/amd/tilapia_fam10/dsdt.asl38
-rw-r--r--src/mainboard/amd/tilapia_fam10/mainboard.c8
-rw-r--r--src/mainboard/amd/torpedo/devicetree.cb120
-rw-r--r--src/mainboard/amd/torpedo/dsdt.asl14
-rw-r--r--src/mainboard/amd/torpedo/gpio.c2
31 files changed, 156 insertions, 156 deletions
diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl
index 9a8469832b..87b0d2169d 100644
--- a/src/mainboard/amd/bettong/acpi/gpe.asl
+++ b/src/mainboard/amd/bettong/acpi/gpe.asl
@@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl
index 37257c42ff..505b519776 100644
--- a/src/mainboard/amd/bettong/dsdt.asl
+++ b/src/mainboard/amd/bettong/dsdt.asl
@@ -45,7 +45,7 @@ DefinitionBlock (
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
- /* global utility methods expected within the \_SB scope */
+ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb
index 0bcc9c16af..ba6a0fafcf 100644
--- a/src/mainboard/amd/bimini_fam10/devicetree.cb
+++ b/src/mainboard/amd/bimini_fam10/devicetree.cb
@@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
+ device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 off end # PCIE P2P bridge 0x960b
@@ -38,7 +38,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
- device pci 14.0 on # SM
+ device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl
index b6a8e17a42..96dc819045 100644
--- a/src/mainboard/amd/bimini_fam10/dsdt.asl
+++ b/src/mainboard/amd/bimini_fam10/dsdt.asl
@@ -234,9 +234,9 @@ DefinitionBlock (
PWMK, 1,
PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@@ -832,7 +832,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -847,13 +847,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -1020,7 +1020,7 @@ DefinitionBlock (
/* PCIe HotPlug event */
/* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
+ * DBGO("\\_GPE\\_L0F\n")
* }
*/
@@ -1043,19 +1043,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
+ * DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
+ * DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
+ * DBGO("\\_GPE\\_L15\n")
* }
*/
@@ -1067,7 +1067,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
+ * DBGO("\\_GPE\\_L17\n")
* }
*/
@@ -1084,7 +1084,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
+ * DBGO("\\_GPE\\_L19\n")
* }
*/
@@ -1115,7 +1115,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
+ * DBGO("\\_GPE\\_L1E\n")
* }
*/
@@ -1125,7 +1125,7 @@ DefinitionBlock (
* }
*/
- } /* End Scope GPE */
+ } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1477,7 +1477,7 @@ DefinitionBlock (
)
#if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@@ -1607,7 +1607,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
+ * Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 0c26416e75..d4397b2372 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable port80 decoding and southbridge poweron init */
sb800_lpc_port80();
- inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */
+ inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */
}
post_code(0x30);
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
index 9a8469832b..87b0d2169d 100644
--- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
@@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/db-ft3b-lc/dsdt.asl b/src/mainboard/amd/db-ft3b-lc/dsdt.asl
index 03d46dcf76..549adc00ec 100644
--- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl
+++ b/src/mainboard/amd/db-ft3b-lc/dsdt.asl
@@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
- /* global utility methods expected within the \_SB scope */
+ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl
index e713ad6688..6429bc604a 100644
--- a/src/mainboard/amd/gardenia/acpi/gpe.asl
+++ b/src/mainboard/amd/gardenia/acpi/gpe.asl
@@ -66,4 +66,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl
index 2f22758712..30e6fdcb3c 100644
--- a/src/mainboard/amd/inagua/acpi/gpe.asl
+++ b/src/mainboard/amd/inagua/acpi/gpe.asl
@@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */
#include "usb_oc.asl"
diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl
index 0069aa9db2..47de049dbc 100644
--- a/src/mainboard/amd/inagua/acpi/sleep.asl
+++ b/src/mainboard/amd/inagua/acpi/sleep.asl
@@ -49,7 +49,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl
index 299d4aa55c..6e9c701a26 100644
--- a/src/mainboard/amd/inagua/acpi/usb_oc.asl
+++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl
@@ -36,7 +36,7 @@ Name(UOM9, 6)
Method(UCOC, 0) {
Sleep(20)
- Store(0x13,CMTI)
+ Store(0x13,CMTI)
Store(0,GPSL)
}
diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl
index c5753eea51..297d9b47cb 100644
--- a/src/mainboard/amd/lamar/acpi/gpe.asl
+++ b/src/mainboard/amd/lamar/acpi/gpe.asl
@@ -70,4 +70,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl
index 2d26a54f6c..f7edfb9119 100644
--- a/src/mainboard/amd/lamar/acpi/sleep.asl
+++ b/src/mainboard/amd/lamar/acpi/sleep.asl
@@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb
index 5000b0c27c..dba1470f33 100644
--- a/src/mainboard/amd/mahogany_fam10/devicetree.cb
+++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb
@@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
+ device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b
@@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
- device pci 14.0 on # SM
+ device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl
index fe2c9869fe..57afc29547 100644
--- a/src/mainboard/amd/mahogany_fam10/dsdt.asl
+++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl
@@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1,
PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */
/* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
+ * DBGO("\\_GPE\\_L0F\n")
* }
*/
@@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
+ * DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
+ * DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
+ * DBGO("\\_GPE\\_L15\n")
* }
*/
@@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
+ * DBGO("\\_GPE\\_L17\n")
* }
*/
@@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
+ * DBGO("\\_GPE\\_L19\n")
* }
*/
@@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
+ * DBGO("\\_GPE\\_L1E\n")
* }
*/
@@ -1131,7 +1131,7 @@ DefinitionBlock (
* }
*/
- } /* End Scope GPE */
+ } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1520,7 +1520,7 @@ DefinitionBlock (
0xF300 /* length */
)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
#if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
@@ -1652,7 +1652,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
+ * Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */
diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl
index 9a8469832b..87b0d2169d 100644
--- a/src/mainboard/amd/olivehill/acpi/gpe.asl
+++ b/src/mainboard/amd/olivehill/acpi/gpe.asl
@@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl
index e70998921c..e2d02087cc 100644
--- a/src/mainboard/amd/olivehill/dsdt.asl
+++ b/src/mainboard/amd/olivehill/dsdt.asl
@@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
- /* global utility methods expected within the \_SB scope */
+ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl
index 9a8469832b..87b0d2169d 100644
--- a/src/mainboard/amd/olivehillplus/acpi/gpe.asl
+++ b/src/mainboard/amd/olivehillplus/acpi/gpe.asl
@@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
index 03d46dcf76..549adc00ec 100644
--- a/src/mainboard/amd/olivehillplus/dsdt.asl
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
- /* global utility methods expected within the \_SB scope */
+ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl
index 8e7840fad5..32d5a2a321 100644
--- a/src/mainboard/amd/parmer/acpi/gpe.asl
+++ b/src/mainboard/amd/parmer/acpi/gpe.asl
@@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl
index 947a2f2d43..d516ccedb0 100644
--- a/src/mainboard/amd/parmer/acpi/sleep.asl
+++ b/src/mainboard/amd/parmer/acpi/sleep.asl
@@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl
index 2f22758712..30e6fdcb3c 100644
--- a/src/mainboard/amd/persimmon/acpi/gpe.asl
+++ b/src/mainboard/amd/persimmon/acpi/gpe.asl
@@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */
#include "usb_oc.asl"
diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl
index 0069aa9db2..47de049dbc 100644
--- a/src/mainboard/amd/persimmon/acpi/sleep.asl
+++ b/src/mainboard/amd/persimmon/acpi/sleep.asl
@@ -49,7 +49,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl
index 8e7840fad5..32d5a2a321 100644
--- a/src/mainboard/amd/thatcher/acpi/gpe.asl
+++ b/src/mainboard/amd/thatcher/acpi/gpe.asl
@@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl
index 1dc590f484..9dd24e42b3 100644
--- a/src/mainboard/amd/thatcher/acpi/sleep.asl
+++ b/src/mainboard/amd/thatcher/acpi/sleep.asl
@@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb
index 77fd875ada..06e33f728d 100644
--- a/src/mainboard/amd/tilapia_fam10/devicetree.cb
+++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb
@@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
+ device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b
@@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
- device pci 14.0 on # SM
+ device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl
index 51128bb218..2151222033 100644
--- a/src/mainboard/amd/tilapia_fam10/dsdt.asl
+++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl
@@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1,
PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */
/* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
+ * DBGO("\\_GPE\\_L0F\n")
* }
*/
@@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
+ * DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
+ * DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
+ * DBGO("\\_GPE\\_L15\n")
* }
*/
@@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
+ * DBGO("\\_GPE\\_L17\n")
* }
*/
@@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
+ * DBGO("\\_GPE\\_L19\n")
* }
*/
@@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
+ * DBGO("\\_GPE\\_L1E\n")
* }
*/
@@ -1131,7 +1131,7 @@ DefinitionBlock (
* }
*/
- } /* End Scope GPE */
+ } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1521,7 +1521,7 @@ DefinitionBlock (
#if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@@ -1655,7 +1655,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
+ * Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 44c1df69ba..5e112158c2 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -24,8 +24,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
@@ -150,7 +150,7 @@ static void set_gpio40_gfx(void)
dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
dword |= (1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
@@ -162,7 +162,7 @@ static void set_gpio40_gfx(void)
dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
dword &= ~(1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb
index 2ce1dfd29e..2adfb27274 100644
--- a/src/mainboard/amd/torpedo/devicetree.cb
+++ b/src/mainboard/amd/torpedo/devicetree.cb
@@ -13,56 +13,56 @@
# GNU General Public License for more details.
#
chip northbridge/amd/agesa/family12/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/agesa/family12
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x1705 inherit
- chip northbridge/amd/agesa/family12 # CPU side of HT root complex
- chip northbridge/amd/agesa/family12 # PCI side of HT root complex
- device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics Bridge
- device pci 1.1 on end # Audio Controller
- device pci 2.0 on end # Root Port
- device pci 3.0 on end # Root Port
- device pci 4.0 on end # PCIE P2P bridge
- device pci 5.0 on end # PCIE P2P bridge
- device pci 6.0 on end # PCIE P2P bridge
- device pci 7.0 on end # PCIE P2P bridge
- device pci 8.0 on end # NB/SB Link P2P bridge
- end # agesa northbridge
- chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
- device pci 10.0 on end # USB XHCI
- device pci 10.1 on end # USB XHCI
- device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.2 on end # USB
- device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- end # SM
- device pci 14.1 on end # IDE
- device pci 14.2 on end # HDA
- device pci 14.3 on # LPC
- chip superio/smsc/kbc1100
- device pnp 2e.7 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- end # kbc1100
- end #LPC
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family12
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x1705 inherit
+ chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family12 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics Bridge
+ device pci 1.1 on end # Audio Controller
+ device pci 2.0 on end # Root Port
+ device pci 3.0 on end # Root Port
+ device pci 4.0 on end # PCIE P2P bridge
+ device pci 5.0 on end # PCIE P2P bridge
+ device pci 6.0 on end # PCIE P2P bridge
+ device pci 7.0 on end # PCIE P2P bridge
+ device pci 8.0 on end # NB/SB Link P2P bridge
+ end # agesa northbridge
+ chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
+ device pci 10.0 on end # USB XHCI
+ device pci 10.1 on end # USB XHCI
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SM
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE
+ device pci 14.2 on end # HDA
+ device pci 14.3 on # LPC
+ chip superio/smsc/kbc1100
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ end # kbc1100
+ end #LPC
device pci 14.4 on end # PCI bridge
- device pci 14.5 on end # USB 2
+ device pci 14.5 on end # USB 2
device pci 14.6 on end # Ethernet Controller
device pci 14.7 on end # SD Flash Controller
device pci 15.0 on end # PCIe PortA
@@ -70,16 +70,16 @@ chip northbridge/amd/agesa/family12/root_complex
device pci 15.2 on end # PCIe PortC
device pci 15.3 on end # PCIe PortD
register "gpp_configuration" = "4" #1:1:1:1
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb900
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 18.5 on end
- device pci 18.6 on end
- device pci 18.7 on end
- end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
- end #domain
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ device pci 18.6 on end
+ device pci 18.7 on end
+ end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+ end #domain
end #northbridge/amd/agesa/family12/root_complex
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl
index 0c55ff4c1b..4ee5fb4ad7 100644
--- a/src/mainboard/amd/torpedo/dsdt.asl
+++ b/src/mainboard/amd/torpedo/dsdt.asl
@@ -676,7 +676,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -691,13 +691,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -766,7 +766,7 @@ DefinitionBlock (
} /* End Method(\_WAK) */
Scope(\_GPE) { /* Start Scope GPE */
- } /* End Scope GPE */
+ } /* End Scope GPE */
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 5a77dc0de0..e26052a734 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -75,7 +75,7 @@ void gpioEarlyInit(void) {
StripInfo = (Data8 & BIT7) >> 7;
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
StripInfo |= (Data8 & BIT7) >> 6;
- if (StripInfo < boardRevC) { // for old board. Rev B
+ if (StripInfo < boardRevC) { // for old board. Rev B
Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
}