diff options
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/dbm690t/dsdt.asl | 13 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/dsdt.asl | 13 |
2 files changed, 12 insertions, 14 deletions
diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 46d3671576..744c687e35 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <southbridge/amd/sb600/sb600.h> + /* DefinitionBlock Statement */ DefinitionBlock ( "DSDT.AML", /* Output filename */ @@ -33,7 +35,6 @@ DefinitionBlock ( Name(PBLN, 0x0) /* Length of BIOS area */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1361,20 +1362,18 @@ DefinitionBlock ( }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - Device(HPTM) { + Device(HPTM) { /* HPET */ Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */ }) Method(_STA, 0) { - Return(0x0F) /* sata is visible */ + Return(0x0F) /* HPET is visible */ } Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) Return(CRS) } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */ } /* end LIBR */ Device(HPBR) { diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 6322289c07..0e8bd05789 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <southbridge/amd/sb600/sb600.h> + /* DefinitionBlock Statement */ DefinitionBlock ( "DSDT.AML", /* Output filename */ @@ -33,7 +35,6 @@ DefinitionBlock ( Name(PBLN, 0x0) /* Length of BIOS area */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1360,20 +1361,18 @@ DefinitionBlock ( }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - Device(HPTM) { + Device(HPTM) { /* HPET */ Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */ }) Method(_STA, 0) { - Return(0x0F) /* sata is visible */ + Return(0x0F) /* HPET is visible */ } Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) Return(CRS) } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */ } /* end LIBR */ Device(HPBR) { |