diff options
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/quartet/Config.lb | 36 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/Config.lb | 81 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/auto.c | 104 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/cmos.layout | 26 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/failover.c | 72 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/mptable.c | 1 |
6 files changed, 189 insertions, 131 deletions
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb index 1a2d8cd09f..d38ab96407 100644 --- a/src/mainboard/amd/quartet/Config.lb +++ b/src/mainboard/amd/quartet/Config.lb @@ -251,19 +251,29 @@ northbridge amd/amdk8 "mc0" pci 1:0.2 on pci 1:1.0 on superio NSC/pc87360 link 1 - pnp 2e.0 - pnp 2e.1 - pnp 2e.2 - pnp 2e.3 - pnp 2e.4 - pnp 2e.5 - pnp 2e.6 - pnp 2e.7 - pnp 2e.8 - pnp 2e.9 - pnp 2e.a - register "com1" = "{1, 0, 0x3f8, 4}" - register "lpt" = "{1}" + pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + pnp 2e.4 off # SWC + pnp 2e.5 off # Mouse + pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + pnp 2e.7 off # GPIO + pnp 2e.8 off # ACB + pnp 2e.9 off # FSCM + pnp 2e.a off # WDT end end end diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb index 1372e46005..bb9044eb0a 100644 --- a/src/mainboard/amd/solo/Config.lb +++ b/src/mainboard/amd/solo/Config.lb @@ -23,6 +23,12 @@ uses XIP_ROM_BASE uses STACK_SIZE uses HEAP_SIZE uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR + ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE=262144 @@ -59,7 +65,14 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## AMD Solo is a 1cpu board +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## AMD Solo is a 1cpu board ## default CONFIG_SMP=1 default CONFIG_MAX_CPUS=1 @@ -152,7 +165,7 @@ object reset.o ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c" + depends "$(MAINBOARD)/failover.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" end @@ -161,13 +174,13 @@ makerule ./failover.inc action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E" end -makerule ./auto.E - depends "$(MAINBOARD)/auto.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h " + action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end -makerule ./auto.inc +makerule ./auto.inc depends "./auto.E ./romcc" - action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" + action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc" end ## @@ -175,18 +188,19 @@ end ## mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc +#mainboardinit cpu/i386/bist32.inc ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## -if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end ### Should this be in the northbridge code? @@ -204,12 +218,12 @@ ldscript /arch/i386/lib/id.lds mainboardinit cpu/k8/earlymtrr.inc ### -### This is the early phase of linuxBIOS startup +### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds + ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end @@ -225,7 +239,7 @@ mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc ## -## Include the secondary Configuration files +## Include the secondary Configuration files ## dir /pc80 config chip.h @@ -254,19 +268,29 @@ northbridge amd/amdk8 "mc0" pci 1:0.2 on # pci 1:1.0 off superio NSC/pc87360 link 1 - pnp 2e.0 - pnp 2e.1 - pnp 2e.2 - pnp 2e.3 - pnp 2e.4 - pnp 2e.5 - pnp 2e.6 - pnp 2e.7 - pnp 2e.8 - pnp 2e.9 - pnp 2e.a - register "com1" = "{1, 0, 0x3f8, 4}" - register "lpt" = "{1}" + pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + pnp 2e.4 off # SWC + pnp 2e.5 off # Mouse + pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + pnp 2e.7 off # GPIO + pnp 2e.8 off # ACB + pnp 2e.9 off # FSCM + pnp 2e.a off # WDT end end end @@ -279,4 +303,5 @@ end ## mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc +#mainboardinit cpu/i386/bist32_fail.inc diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c index 5963934fd5..3a80e4c1bd 100644 --- a/src/mainboard/amd/solo/auto.c +++ b/src/mainboard/amd/solo/auto.c @@ -1,14 +1,16 @@ #define ASSEMBLY 1 #include <stdint.h> #include <device/pci_def.h> -#include <cpu/p6/apic.h> #include <arch/io.h> #include <device/pnp.h> #include <arch/romcc_io.h> +#include <arch/smp/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/early_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/k8/apic_timer.c" @@ -17,9 +19,26 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" #include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/NSC/pc87360/pc87360_early_serial.c" #define SIO_BASE 0x2e +static void hard_reset(void) +{ + set_bios_reset(); + + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1); +} + static void memreset_setup(void) { if (is_cpu_pre_c0()) { @@ -54,7 +73,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) static inline void activate_spd_rom(const struct mem_controller *ctrl) { - /* nothing here */ + /* nothing to do */ } static inline int spd_read_byte(unsigned device, unsigned address) @@ -62,69 +81,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* no specific code here. this should go away completely */ -static void coherent_ht_mainboard(unsigned cpus) -{ -} #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" -static void enable_lapic(void) -{ - - msr_t msr; - msr = rdmsr(0x1b); - msr.hi &= 0xffffff00; - msr.lo &= 0x000007ff; - msr.lo |= APIC_DEFAULT_BASE | (1 << 11); - wrmsr(0x1b, msr); -} - -static void stop_this_cpu(void) -{ - unsigned apicid; - apicid = apic_read(APIC_ID) >> 24; - - /* Send an APIC INIT to myself */ - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); - /* Wait for the ipi send to finish */ - apic_wait_icr_idle(); - - /* Deassert the APIC INIT */ - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); - /* Wait for the ipi send to finish */ - apic_wait_icr_idle(); - - /* If I haven't halted spin forever */ - for(;;) { - hlt(); - } -} - -#define PC87360_FDC 0x00 -#define PC87360_PP 0x01 -#define PC87360_SP2 0x02 -#define PC87360_SP1 0x03 -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 -#define PC87360_KBCK 0x06 -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -/* FIXME: Do we really need this on Solo boards? */ -static void pc87360_enable_serial(void) -{ - pnp_set_logical_device(SIO_BASE, PC87360_SP1); - pnp_set_enable(SIO_BASE, 1); - pnp_set_iobase0(SIO_BASE, 0x3f8); -} - static void main(void) { static const struct mem_controller cpu[] = { @@ -138,26 +99,29 @@ static void main(void) .channel1 = { 0, 0, 0, 0 }, } }; + int needs_reset; + enable_lapic(); + init_timer(); if (cpu_init_detected()) { asm("jmp __cpu_reset"); } enable_lapic(); init_timer(); - -#if 0 - /* Enabling this will make romcc segfault - 2003/10/13 */ + distinguish_cpu_resets(); if (!boot_cpu()) { print_err("This LinuxBIOS image is built for UP only.\n"); + stop_this_cpu(); } -#endif - pc87360_enable_serial(); + pc87360_enable_serial(SIO_BASE, TTYS0_BASE); uart_init(); console_init(); setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); - + needs_reset = setup_coherent_ht_domain(); + needs_reset = ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); + if (needs_reset) { + print_info("ht reset -"); + soft_reset(); + } #if 0 print_pci_devices(); #endif diff --git a/src/mainboard/amd/solo/cmos.layout b/src/mainboard/amd/solo/cmos.layout index 5ba4c032c1..247715e6ac 100644 --- a/src/mainboard/amd/solo/cmos.layout +++ b/src/mainboard/amd/solo/cmos.layout @@ -29,6 +29,9 @@ entries 386 1 e 1 ECC_memory 388 4 r 0 reboot_bits 392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first @@ -36,7 +39,14 @@ entries 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -1008 16 h 0 check_sum +440 4 e 9 slow_cpu +444 1 e 1 nmi +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + enumerations @@ -66,9 +76,21 @@ enumerations 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums -checksum 392 1007 1008 +checksum 392 983 984 diff --git a/src/mainboard/amd/solo/failover.c b/src/mainboard/amd/solo/failover.c index bd9c17020e..bd5869fead 100644 --- a/src/mainboard/amd/solo/failover.c +++ b/src/mainboard/amd/solo/failover.c @@ -3,40 +3,78 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> -#include "arch/romcc_io.h" +#include <arch/romcc_io.h> +#include <arch/smp/lapic.h> #include "pc80/mc146818rtc_early.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #include "cpu/p6/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" +#define HAVE_REGPARM_SUPPORT 0 +#if HAVE_REGPARM_SUPPORT +static unsigned long main(unsigned long bist) +{ +#else static void main(void) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(0); + unsigned long bist = 0; +#endif + /* Make cerain my local apic is useable */ + enable_lapic(); - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Is this a cpu reset? */ + /* Is this a cpu only reset? */ if (cpu_init_detected()) { if (last_boot_normal()) { - asm("jmp __normal_image"); + goto normal_image; } else { - asm("jmp __cpu_reset"); + goto cpu_reset; } } - /* Is this a deliberate reset by the bios */ - else if (bios_reset_detected() && last_boot_normal()) { - asm("jmp __normal_image"); - } /* Is this a secondary cpu? */ - else if (!boot_cpu() && last_boot_normal()) { - asm("jmp __normal_image"); + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(0); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; } /* This is the primary cpu how should I boot? */ else if (do_normal_boot()) { - asm("jmp __normal_image"); + goto normal_image; + } + else { + goto fallback_image; } + normal_image: + asm("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: +#if HAVE_REGPARM_SUPPORT + return bist; +#else + return; +#endif } diff --git a/src/mainboard/amd/solo/mptable.c b/src/mainboard/amd/solo/mptable.c index dfe4320181..42c2e6b33c 100644 --- a/src/mainboard/amd/solo/mptable.c +++ b/src/mainboard/amd/solo/mptable.c @@ -178,7 +178,6 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) 1, (5<<2)|1, 0x02, 0x11); - /* There is no extension information... */ /* Compute the checksums */ |