summaryrefslogtreecommitdiff
path: root/src/mainboard/apple/macbook21/early_init.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/apple/macbook21/early_init.c')
-rw-r--r--src/mainboard/apple/macbook21/early_init.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/apple/macbook21/early_init.c b/src/mainboard/apple/macbook21/early_init.c
new file mode 100644
index 0000000000..d4654de118
--- /dev/null
+++ b/src/mainboard/apple/macbook21/early_init.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/i945/i945.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+void mainboard_late_rcba_config(void)
+{
+ /* V0CTL Virtual Channel 0 Resource Control */
+ RCBA32(0x0014) = 0x80000001;
+
+ /* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042210;
+ RCBA32(0x3108) = 0x10004321;
+
+ /* PCIe Interrupts */
+ RCBA32(D28IP) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(D27IP) = 0x00000001;
+
+ /* dev irq route register */
+ RCBA16(D31IR) = 0x0232;
+ RCBA16(D30IR) = 0x3246;
+ RCBA16(D29IR) = 0x0235;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x3216;
+
+ /* Disable unused devices */
+ RCBA32(FD) |= FD_INTLAN;
+
+ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(0x1e9c) = 0x000200f0;
+ RCBA32(0x1e98) = 0x000c0801;
+}