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-rw-r--r--src/mainboard/artecgroup/dbe61/Kconfig8
-rw-r--r--src/mainboard/artecgroup/dbe61/romstage.c53
2 files changed, 16 insertions, 45 deletions
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
index 62470f479c..6803b93756 100644
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ b/src/mainboard/artecgroup/dbe61/Kconfig
@@ -31,7 +31,7 @@ config IRQ_SLOT_COUNT
default 3
depends on BOARD_ARTECGROUP_DBE61
-config RAMBASE
- hex
- default 0x4000
- depends on BOARD_ARTECGROUP_DBE61
+#config RAMBASE
+# hex
+# default 0x4000
+## depends on BOARD_ARTECGROUP_DBE61
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 29120136a6..07fd548722 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -45,9 +45,9 @@ static int spd_read_byte(unsigned device, unsigned address)
{
int i;
- if (device == DIMM0){
- for (i=0; i < (ARRAY_SIZE(spd_table)); i++){
- if (spd_table[i].address == address){
+ if (device == DIMM0) {
+ for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
+ if (spd_table[i].address == address) {
return spd_table[i].data;
}
}
@@ -69,46 +69,14 @@ static int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
- u32 msrnum;
- msr_t msr;
-};
-
-static const struct msrinit msr_table[] =
-{
- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
- * Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Serialize, Cache Disable.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
- {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
- {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
- {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
- {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(msr_table); i++)
- wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -137,6 +105,9 @@ void cache_as_ram_main(void)
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
@@ -144,8 +115,7 @@ void cache_as_ram_main(void)
sdram_initialize(1, memctrl);
/* Dump memory configuratation */
- /*{
- msr_t msr;
+#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
print_debug_hex32(MC_CF07_DATA);
@@ -173,9 +143,10 @@ void cache_as_ram_main(void)
print_debug_hex32(msr.lo);
msr = rdmsr(MC_CF8F_DATA);
print_debug(" \n");
- }*/
+#endif
/* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
+ // ram_check(0x00000000, 640 * 1024);
+ // ram_check(1024 * 1024, 2 * 1024 * 1024);
}