diff options
Diffstat (limited to 'src/mainboard/asi/mb_5blmp/Config.lb')
| -rw-r--r-- | src/mainboard/asi/mb_5blmp/Config.lb | 209 |
1 files changed, 209 insertions, 0 deletions
diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb new file mode 100644 index 0000000000..8178a8caf9 --- /dev/null +++ b/src/mainboard/asi/mb_5blmp/Config.lb @@ -0,0 +1,209 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +## +## Romcc output +## +# makerule ./failover.E +# depends "$(MAINBOARD)/failover.c ./romcc" +# action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +# end +# +# makerule ./failover.inc +# depends "$(MAINBOARD)/failover.c ./romcc" +# action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +# end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +# if USE_FALLBACK_IMAGE +# ldscript /arch/i386/lib/failover.lds +# mainboardinit ./failover.inc +# end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 # Southbridge + device pci 12.0 on + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.0 on # PIC + io 0x60 = 0x20 + io 0x62 = 0xa0 + irq 0x70 = 2 + end + device pnp 2e.1 on # DMA + end + device pnp 2e.2 on # System Timer + io 0x60 = 0x40 + irq 0x70 = 0 + end + device pnp 2e.3 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.4 on # Keyboard + Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.5 on # PC Speaker + end + device pnp 2e.6 on # Math Coprocessor (FPU) + io 0x60 = 0xf0 + irq 0x70 = 13 + end + device pnp 2e.7 on # System board + end + device pnp 2e.8 on # Motherboard resources + end + device pnp 2e.9 on # PCI bus + end + device pnp 2e.c on # Motherboard resources + end + device pnp 2e.d on # Motherboard resources + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.f off # FDC + end + device pnp 2e.10 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.12 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 off end # Audio + device pci 12.4 off end # Video (VGA) + end + # device pci 12.4 on # VGA (onboard) + # chip drivers/pci/onboard + # device pci 12.4 on end + # register "rom_address" = "0xfffc0000" # 256 KB image + # # register "rom_address" = "0xfff80000" # 512 KB image + # # register "rom_address" = "0xfff00000" # 1 MB image + # end + # end + device pci 0f.0 off end # Ethernet (Realtek RTL8139B) + device pci 13.0 on end # USB + end + end + + chip cpu/amd/model_gx1 # CPU + end + +end + |