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-rw-r--r--src/mainboard/asrock/g41c-gs/Kconfig17
-rw-r--r--src/mainboard/asrock/g41c-gs/Kconfig.name3
-rw-r--r--src/mainboard/asrock/g41c-gs/gpio.c13
-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c28
-rw-r--r--src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb (renamed from src/mainboard/asrock/g41c-gs/devicetree.cb)0
-rw-r--r--src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb138
6 files changed, 185 insertions, 14 deletions
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig
index ac4520147d..1139be6093 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig
+++ b/src/mainboard/asrock/g41c-gs/Kconfig
@@ -14,7 +14,7 @@
# GNU General Public License for more details.
#
-if BOARD_ASROCK_G41C_GS_R2_0
+if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -22,7 +22,8 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_X4X
select SOUTHBRIDGE_INTEL_I82801GX
- select SUPERIO_NUVOTON_NCT6776
+ select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
+ select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select PCIEXP_ASPM
@@ -41,10 +42,20 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
- default "G41C-GS R2.0"
+ default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
+ default "G41C-GS" if BOARD_ASROCK_G41C_GS
+
+config DEVICETREE
+ string
+ default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
+ default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
config MAX_CPUS
int
default 4
+# Override the default variant behavior, since the data.vbt is the same
+config INTEL_GMA_VBT_FILE
+ default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
+
endif # BOARD_ASROCK_G41C_GS_R2_0
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name
index 5cf58879bd..5ce5aa70f2 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig.name
+++ b/src/mainboard/asrock/g41c-gs/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_ASROCK_G41C_GS_R2_0
bool "G41C-GS R2.0"
+
+config BOARD_ASROCK_G41C_GS
+ bool "G41C-GS / G41C-S"
diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/gpio.c
index 6299d62dae..be0b66da89 100644
--- a/src/mainboard/asrock/g41c-gs/gpio.c
+++ b/src/mainboard/asrock/g41c-gs/gpio.c
@@ -57,6 +57,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio28 = GPIO_DIR_INPUT,
};
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio10 = GPIO_LEVEL_LOW,
.gpio15 = GPIO_LEVEL_LOW,
@@ -67,6 +68,18 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio25 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
};
+#else /* BOARD_ASROCK_G41C_GS */
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio10 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_LOW,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+};
+#endif
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 4498b10706..e1f4152a4d 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -22,6 +22,8 @@
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <superio/nuvoton/nct6776/nct6776.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+#include <superio/winbond/common/winbond.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <lib.h>
#include <arch/stages.h>
@@ -30,7 +32,8 @@
#include <device/pnp_def.h>
#include <timestamp.h>
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
+#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -44,15 +47,19 @@ static void mb_lpc_setup(void)
setup_pch_gpios(&mainboard_gpio_map);
/* Set GPIOs on superio, enable UART */
- nuvoton_pnp_enter_conf_state(SERIAL_DEV);
- pnp_set_logical_device(SERIAL_DEV);
-
- pnp_write_config(SERIAL_DEV, 0x1c, 0x80);
- pnp_write_config(SERIAL_DEV, 0x27, 0x80);
- pnp_write_config(SERIAL_DEV, 0x2a, 0x60);
-
- nuvoton_pnp_exit_conf_state(SERIAL_DEV);
-
+ if (IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)) {
+ nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
+ pnp_set_logical_device(SERIAL_DEV_R2);
+
+ pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
+ pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
+ pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);
+
+ nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
+ nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
+ } else { /* BOARD_ASROCK_G41C_GS */
+ winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
+ }
/* IRQ routing */
RCBA16(D31IR) = 0x0132;
RCBA16(D29IR) = 0x0237;
@@ -91,7 +98,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
mb_lpc_setup();
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/asrock/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
index f58fae749c..f58fae749c 100644
--- a/src/mainboard/asrock/g41c-gs/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
new file mode 100644
index 0000000000..805f2dac93
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
@@ -0,0 +1,138 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on # PCI domain
+ subsystemid 0x1458 0x5000 inherit
+ device pci 0.0 on # Host Bridge
+ subsystemid 0x1849 0x2e30
+ end
+ device pci 1.0 on end # PEG
+
+ device pci 2.0 on # Integrated graphics controller
+ subsystemid 0x1849 0x2e32
+ end
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801gx # Southbridge
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x0b"
+
+ register "ide_enable_primary" = "0x1"
+ register "gpe0_en" = "0x440"
+
+ device pci 1b.0 on # Audio
+ subsystemid 0x1849 0x3662
+ end
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on # USB
+ subsystemid 0x1849 0x27c8
+ end
+ device pci 1d.1 on # USB
+ subsystemid 0x1849 0x27c9
+ end
+ device pci 1d.2 on # USB
+ subsystemid 0x1849 0x27ca
+ end
+ device pci 1d.3 on # USB
+ subsystemid 0x1849 0x27cb
+ end
+ device pci 1d.7 on # USB
+ subsystemid 0x1849 0x27cc
+ end
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 off end # AC'97 Audio
+ device pci 1e.3 off end # AC'97 Modem
+ device pci 1f.0 on # ISA bridge
+ subsystemid 0x1849 0x27b8
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # Parallel port
+ # global
+ irq 0x28 = 0x70
+ irq 0x2c = 0xd2
+ # parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2
+ device pnp 2e.5 on # Keyboard & MOUSE
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 0x0C
+ end
+ device pnp 2e.6 off end # SPI
+ device pnp 2e.7 off end # GPIO6
+ device pnp 2e.8 off end # WDT0#, PLED
+ device pnp 2e.9 off end # GPIO2
+ device pnp 2e.109 off end # GPIO3
+ device pnp 2e.209 on # GPIO4
+ irq 0xf4 = 0x73
+ end
+ device pnp 2e.309 off end # GPIO5
+ device pnp 2e.a on # ACPI
+ irq 0xe4 = 0x10 # Power dram during s3
+ end
+ device pnp 2e.b on # HWM, front pannel LED
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ device pnp 2e.c off end # PECI, SST
+ end
+ end
+ device pci 1f.1 on # PATA/IDE
+ subsystemid 0x1849 0x27df
+ end
+ device pci 1f.2 on # SATA
+ subsystemid 0x1849 0x27c0
+ end
+ device pci 1f.3 on # SMbus
+ subsystemid 0x1849 0x27da
+ chip drivers/i2c/ck505 # W83115RG-965
+ # set SATA to fixed 100Mhz refclk
+ register "mask" = "{ 0x02 }"
+ register "regs" = "{ 0x02 }"
+ device i2c 69 on end
+ end
+ end
+ end
+ end
+end