diff options
Diffstat (limited to 'src/mainboard/asrock/imb-a180/mptable.c')
| -rw-r--r-- | src/mainboard/asrock/imb-a180/mptable.c | 44 |
1 files changed, 21 insertions, 23 deletions
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index a8326a02a4..11da1309a0 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -29,8 +29,6 @@ #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ #define IO_APIC_ID CONFIG_MAX_CPUS -extern u8 bus_yangtze[6]; - extern u32 apicid_yangtze; u8 picr_data[0x54] = { @@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14); - PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15); - PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16); - PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15); - PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16); - PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17); - PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16); - PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17); - PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14); - PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12); - PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13); - PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14); + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); |