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-rw-r--r--src/mainboard/asrock/e350m1/romstage.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7d25ec1d38..61de9f6ee8 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -55,23 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr(0xc0010062, 0);
- // early enable of PrefetchEnSPIFromHost
- if (boot_cpu()) {
- __outdword(0xcf8, 0x8000a3b8);
- __outdword(0xcfc, __indword(0xcfc) | 1 << 24);
- }
- // early enable of SPI 33 MHz fast mode read
- if (boot_cpu()) {
- volatile u32 *spiBase = (void *)0xa0000000;
- u32 save;
- __outdword(0xcf8, 0x8000a3a0);
- save = __indword(0xcfc);
- __outdword(0xcfc, (u32) spiBase | 2); // set temp MMIO base
- spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14);
- spiBase[0] |= 1 << 18; // fast read enable
- __outdword(0xcfc, save); // clear temp base
- }
-
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();