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-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c4
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c3
2 files changed, 2 insertions, 5 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index de73d016d3..7a2004f141 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -19,7 +19,6 @@
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
-#include <cpu/x86/bist.h>
#include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/common/gpio.h>
@@ -82,7 +81,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -95,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
- report_bist_failure(bist);
enable_smbus();
x4x_early_init();
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 3af82f2907..91667ded57 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -39,7 +39,7 @@ static const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG,
};
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@@ -94,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist)
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0],
- .bist = bist,
};
romstage_common(&romstage_params);