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-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 0605ef1245..ab6b1d88ae 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -15,17 +15,18 @@
* GNU General Public License for more details.
*/
+#include <arch/io.h>
#include <console/console.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/bist.h>
+#include <northbridge/intel/x4x/iomap.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <northbridge/intel/x4x/iomap.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)