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-rw-r--r--src/mainboard/asus/h61-series/Kconfig12
-rw-r--r--src/mainboard/asus/h61-series/Kconfig.name12
-rw-r--r--src/mainboard/asus/h61-series/acpi/superio.asl15
-rw-r--r--src/mainboard/asus/h61-series/dsdt.asl8
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/board_info.txt7
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.default6
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout73
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/data.vbtbin0 -> 3902 bytes
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb115
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c38
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/gma-mainboard.ads15
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/gpio.c126
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c29
13 files changed, 455 insertions, 1 deletions
diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index 212c06b33d..cadc9841de 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -20,12 +20,14 @@ config MAINBOARD_DIR
config VARIANT_DIR
string
default "h61m-cs" if BOARD_ASUS_H61M_CS
+ default "p8h61-m_lx" if BOARD_ASUS_P8H61_M_LX
default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO
config MAINBOARD_PART_NUMBER
string
default "H61M-CS" if BOARD_ASUS_H61M_CS
+ default "P8H61-M LX" if BOARD_ASUS_P8H61_M_LX
default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO
@@ -39,4 +41,14 @@ config CMOS_DEFAULT_FILE
config CMOS_LAYOUT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
+#
+# These ME partitions need to be whitelisted for correct system
+# operation. Example issues from removing them include: no serial output
+# and kernel warnings about loading audio codecs.
+#
+config ME_CLEANER_ARGS
+ string
+ depends on USE_ME_CLEANER
+ default "-S --whitelist EFFS,FCRS" if BOARD_ASUS_P8H61_M_LX
+
endif
diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name
index 6bb8d45743..c53118856f 100644
--- a/src/mainboard/asus/h61-series/Kconfig.name
+++ b/src/mainboard/asus/h61-series/Kconfig.name
@@ -8,6 +8,18 @@ config BOARD_ASUS_H61M_CS
select NO_UART_ON_SUPERIO
select SUPERIO_NUVOTON_NCT6779D
+config BOARD_ASUS_P8H61_M_LX
+ bool "P8H61-M LX"
+ select BOARD_ASUS_H61_SERIES
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_INT15
+ select REALTEK_8168_RESET
+ select RT8168_SET_LED_MODE
+ select SUPERIO_NUVOTON_COMMON_COM_A
+ select SUPERIO_NUVOTON_NCT6776
+
config BOARD_ASUS_P8H61_M_LX3_R2_0
bool "P8H61-M LX3 R2.0"
select BOARD_ASUS_H61_SERIES
diff --git a/src/mainboard/asus/h61-series/acpi/superio.asl b/src/mainboard/asus/h61-series/acpi/superio.asl
index ee2eabeb75..55816266cf 100644
--- a/src/mainboard/asus/h61-series/acpi/superio.asl
+++ b/src/mainboard/asus/h61-series/acpi/superio.asl
@@ -1,3 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#if CONFIG(BOARD_ASUS_P8H61_M_LX)
+
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define NCT6776_SHOW_PP
+#define NCT6776_SHOW_SP1
+#define NCT6776_SHOW_KBC
+#define NCT6776_SHOW_HWM
+
+#undef NCT6776_SHOW_GPIO
+
+#include <superio/nuvoton/nct6776/acpi/superio.asl>
+
+#else /* !BOARD_ASUS_P8H61_M_LX */
#include <drivers/pc80/pc/ps2_controller.asl>
+#endif
diff --git a/src/mainboard/asus/h61-series/dsdt.asl b/src/mainboard/asus/h61-series/dsdt.asl
index e8e2b3a3e5..539922e181 100644
--- a/src/mainboard/asus/h61-series/dsdt.asl
+++ b/src/mainboard/asus/h61-series/dsdt.asl
@@ -2,13 +2,19 @@
#include <acpi/acpi.h>
+#if CONFIG(BOARD_ASUS_P8H61_M_LX)
+#define BOARD_DSDT_REVISION 0x20171231 /* OEM revision */
+#else
+#define BOARD_DSDT_REVISION 0x20141018
+#endif
+
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
- 0x20141018 /* OEM revision */
+ BOARD_DSDT_REVISION
)
{
#include <acpi/dsdt_top.asl>
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/board_info.txt
new file mode 100644
index 0000000000..9c7f9721b1
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P8H61M_LX/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.default b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.default
new file mode 100644
index 0000000000..d3812abb15
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=64M
+nmi=Enable
+power_on_after_fail=Disable
+sata_mode=AHCI
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout
new file mode 100644
index 0000000000..782a1b8c10
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout
@@ -0,0 +1,73 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 4 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# coreboot config options: northbridge
+412 3 e 7 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+
+2 0 Enable
+2 1 Disable
+
+3 0 Fallback
+3 1 Normal
+
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+6 0 AHCI
+6 1 Compatible
+
+7 0 32M
+7 1 64M
+7 2 96M
+7 3 128M
+7 4 160M
+7 5 192M
+7 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/data.vbt b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/data.vbt
new file mode 100644
index 0000000000..7eda3ab04d
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb
new file mode 100644
index 0000000000..276119051c
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb
@@ -0,0 +1,115 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "acpi_c1" = "1"
+ register "acpi_c2" = "3"
+ register "acpi_c3" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1043 0x844d inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe bridge for discrete graphics
+ device pci 02.0 on end # VGA controller
+
+ chip southbridge/intel/bd82x6x
+ register "c2_latency" = "101"
+ register "gen1_dec" = "0x00000295" # Super I/O HWM
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device pci 16.0 on end # Management Engine interface 1
+ device pci 16.1 off end # Management Engine interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on # HD audio controller
+ subsystemid 0x1043 0x8445
+ end
+ device pci 1c.0 on end # PCIe 1x slot (PCIEX1_1)
+ device pci 1c.1 on end # PCIe 1x slot (PCIEX1_2)
+ device pci 1c.2 on # Realtek Gigabit Ethernet
+ subsystemid 0x1043 0x8432
+ chip drivers/net
+ register "customized_leds" = "0x00f6"
+ device pci 00.0 on end
+ end
+ end
+ device pci 1c.3 off end # Unused PCIe port
+ device pci 1c.4 on end # PCIe 1x slot (PCIEX1_3)
+ device pci 1c.5 off end # Unused PCIe port
+ device pci 1c.6 off end # Unused PCIe port
+ device pci 1c.7 off end # Unused PCIe port
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/nuvoton/nct6776
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # Parallel
+ io 0x60 = 0x0378
+ irq 0x70 = 7
+ drq 0x74 = 4 # No DMA
+ irq 0xf0 = 0x3c # Printer mode
+ end
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x03f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # PS/2 KBC
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 1 # Keyboard
+ irq 0x72 = 12 # Mouse
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO8
+ device pnp 2e.107 off end # GPIO9
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.108 off end # GPIO0
+ device pnp 2e.208 off end # GPIOA
+ device pnp 2e.308 off end # GPIO base
+ device pnp 2e.109 off end # GPIO1
+ device pnp 2e.209 off end # GPIO2
+ device pnp 2e.309 off end # GPIO3
+ device pnp 2e.409 off end # GPIO4
+ device pnp 2e.509 off end # GPIO5
+ device pnp 2e.609 off end # GPIO6
+ device pnp 2e.709 off end # GPIO7
+ device pnp 2e.a on # ACPI
+ # Power RAM in S3.
+ irq 0xe4 = 0x10
+ end
+ device pnp 2e.b on # HWM, LED
+ io 0x60 = 0x0290
+ io 0x62 = 0x0200
+
+ # Global registers to select
+ # HWM/LED functions instead of
+ # floppy functions.
+ irq 0x1c = 0x03
+ irq 0x24 = 0x24
+ end
+ device pnp 2e.d off end # VID
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f off end # GPIO PP/OD
+ device pnp 2e.14 off end # SVID
+ device pnp 2e.16 off end # Deep sleep
+ device pnp 2e.17 off end # GPIOA
+ end
+ end
+ device pci 1f.2 on end # SATA controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c
new file mode 100644
index 0000000000..5e54d08e85
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <device/dram/ddr3.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/gma-mainboard.ads
new file mode 100644
index 0000000000..c6422a5ca2
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/gma-mainboard.ads
@@ -0,0 +1,15 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/gpio.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/gpio.c
new file mode 100644
index 0000000000..18ee191a40
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/gpio.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio31 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
new file mode 100644
index 0000000000..3b707c2cd4
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <stdint.h>
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Realtek ALC887-VD */
+ 0x10438445, /* Subsystem ID */
+ 15, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x10438445),
+ AZALIA_PIN_CFG(0, 0x11, 0x99430130),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-11 10:21:49 +0000