diff options
Diffstat (limited to 'src/mainboard/asus/m2v-mx_se')
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/Kconfig | 70 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/Kconfig.name | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/acpi_tables.c | 68 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/board_info.txt | 7 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/cmos.default | 11 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/cmos.layout | 60 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/devicetree.cb | 77 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/dsdt.asl | 241 | ||||
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/romstage.c | 183 |
9 files changed, 0 insertions, 719 deletions
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig deleted file mode 100644 index 60ed865fad..0000000000 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Cristi Măgherușan <cristi.magherusan@net.utcluj.ro> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_M2V_MX_SE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_AM2 - select DIMM_DDR2 - select QRANK_DIMM_SUPPORT - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SOUTHBRIDGE_VIA_SUBTYPE_K8M890 - select SUPERIO_ITE_IT8712F - select HAVE_OPTION_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_512 - select VGA - select HAVE_ACPI_RESUME - select SET_FIDVID - -config MAINBOARD_DIR - string - default asus/m2v-mx_se - -config DCACHE_RAM_BASE - hex - default 0xcc000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 - -config APIC_ID_OFFSET - hex - default 0x10 - -config MAINBOARD_PART_NUMBER - string - default "M2V-MX SE" - -config MAX_CPUS - int - default 2 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -endif # BOARD_ASUS_M2V_MX_SE diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig.name b/src/mainboard/asus/m2v-mx_se/Kconfig.name deleted file mode 100644 index f15d444131..0000000000 --- a/src/mainboard/asus/m2v-mx_se/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_M2V_MX_SE - bool "M2V-MX SE" diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c deleted file mode 100644 index 397d310a99..0000000000 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by - * - * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> - * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> - * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/device.h> -#include <device/pci_ids.h> -#include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" -#include "northbridge/amd/amdk8/acpi.h" -#include <cpu/amd/powernow.h> -#include <cpu/amd/amdk8_sysconf.h> - -void get_bus_conf(void) -{ - /* FIXME: implement this. */ -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - unsigned int gsi_base = 0x18; - - /* Create all subtables for processors. */ - current = acpi_create_madt_lapics(current); - - /* Write SB IOAPIC. */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - VT8237R_APIC_ID, IO_APIC_ADDR, 0); - - /* Write NB IOAPIC. */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); - - /* IRQ9 ACPI active low. */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - - /* IRQ0 -> APIC IRQ2. */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); - - /* Create all subtables for processors. */ - current = acpi_create_madt_lapic_nmis(current, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); - - return current; -} diff --git a/src/mainboard/asus/m2v-mx_se/board_info.txt b/src/mainboard/asus/m2v-mx_se/board_info.txt deleted file mode 100644 index 00139ad873..0000000000 --- a/src/mainboard/asus/m2v-mx_se/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2VMX_SE/ -ROM package: DIP8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2007 diff --git a/src/mainboard/asus/m2v-mx_se/cmos.default b/src/mainboard/asus/m2v-mx_se/cmos.default deleted file mode 100644 index fae766bc88..0000000000 --- a/src/mainboard/asus/m2v-mx_se/cmos.default +++ /dev/null @@ -1,11 +0,0 @@ -boot_option = Fallback -hw_scrubber = Enable -interleave_chip_selects = Enable -max_mem_clock = DDR2-400 -multi_core = Enable -power_on_after_fail = On -debug_level = Spew -slow_cpu = off -nmi = Disable -videoram_size = 8MB -iommu = Enable diff --git a/src/mainboard/asus/m2v-mx_se/cmos.layout b/src/mainboard/asus/m2v-mx_se/cmos.layout deleted file mode 100644 index 29476ecc33..0000000000 --- a/src/mainboard/asus/m2v-mx_se/cmos.layout +++ /dev/null @@ -1,60 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -448 3 e 10 videoram_size -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -# videoram_size: mimics the bits in the ramcontroller. -10 1 8MB -10 2 16MB -10 3 32MB -10 4 64MB -10 5 128MB -10 6 256MB - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb deleted file mode 100644 index 213e3ea9c0..0000000000 --- a/src/mainboard/asus/m2v-mx_se/devicetree.cb +++ /dev/null @@ -1,77 +0,0 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x1d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR - end - end - device pci 12.0 on end # VIA LAN - device pci 13.0 on end # br - device pci 13.1 on end # br2 need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8M890 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl deleted file mode 100644 index 30ce550996..0000000000 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ /dev/null @@ -1,241 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> - * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) -{ - #include "northbridge/amd/amdk8/util.asl" - - #include <southbridge/via/k8t890/acpi/sleepstates.asl> - - /* blink a LED when entering the sleep (any type) */ - Method (_PTS, 1, NotSerialized) - { - Store (0x1, \_SB.PCI0.ISA.LEDR) - } - - /* cancel a LED blinking when waking from sleep (any type) */ - Method (_WAK, 1, NotSerialized) - { - Store (0x0, \_SB.PCI0.ISA.LEDR) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) - } - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - /* Top PCI device */ - Device (PCI0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) - Name (_UID, 0x00) - Name (_BBN, 0x00) - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length - ,, , TypeStatic) - }) - /* Methods bellow use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - */ - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - /* PCI Routing Table */ - Name (_PRT, Package () { - Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */ - Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ - Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 }, /* USB routing */ - Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 }, - Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 }, - Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */ - Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */ - Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */ - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ - }) - - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00130000) - Name (_UID, 0x00) - Name (_BBN, 0x4) - Name (_PRT, Package () { - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */ - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 }, - }) - } - - Device (TBRG) - { - Name (_ADR, 0x00130001) - Name (_UID, 0x00) - Name (_BBN, 0x5) - Name (_PRT, Package () { - Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */ - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 }, - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */ - Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 }, - }) - } - Device (ISA) { - Name (_ADR, 0x00110000) - OperationRegion (PCIC, PCI_Config, 0x0, 0xff) - Field (PCIC, ByteAcc, NoLock, Preserve) - { - Offset (0x94), - /* two LSB bits are blink rate */ - LEDR, 2, - } - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - - /* PS/2 floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) - IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } - } - /* Dummy device to hold auto generated reserved resources */ - Device(MBRS) { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - External(_CRS) /* Resource Template in SSDT */ - } - } - } -} diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c deleted file mode 100644 index 322f76302f..0000000000 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) - * Copyright (C) 2006 MSI - * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) - * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -unsigned int get_sbdn(unsigned bus); - -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/amd/mtrr.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include <halt.h> -#include <northbridge/amd/amdk8/raminit.h> -#include <delay.h> - -#include <superio/ite/common/ite.h> -#include <superio/ite/it8712f/it8712f.h> -#include <southbridge/via/vt8237r/vt8237r.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include <spd.h> -#include <northbridge/amd/amdk8/f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -void memreset(int controllers, const struct mem_controller *ctrl) { } -void activate_spd_rom(const struct mem_controller *ctrl) { } - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "southbridge/via/k8t890/early_car.c" -#include <northbridge/amd/amdk8/amdk8.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/model_fxx/init_cpus.c" - -#define SB_VFSMAF 0 - -static void ldtstop_sb(void) -{ - printk(BIOS_DEBUG, "toggle LDTSTP#\n"); - - /* fix errata #181, disable DRAM controller it will get enabled later */ - u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94); - tmp |= (( 1 << 14) | (1 << 3)); - pci_write_config8(PCI_DEV(0, 0x18, 2), 0x94, tmp); - - u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); - reg = reg ^ (1 << 0); - outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); - reg = inb(VT8237R_ACPI_IO_BASE + 0x15); - printk(BIOS_DEBUG, "done\n"); -} - -#include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/resourcemap.c" - -void do_soft_reset(void) -{ - uint8_t tmp; - - set_bios_reset(); - printk(BIOS_DEBUG, "soft reset\n"); - - /* PCI reset */ - tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); - tmp |= 0x01; - /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ - pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - - halt(); -} - -unsigned int get_sbdn(unsigned bus) -{ - pci_devfn_t dev; - - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); - return (dev >> 15) & 0x1f; -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr[] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, - }; - unsigned bsp_apicid = 0; - int needs_reset = 0; - struct sys_info *sysinfo = &sysinfo_car; - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_kill_watchdog(GPIO_DEV); - ite_enable_3vsbsw(GPIO_DEV); - console_init(); - enable_rom_decode(); - - printk(BIOS_INFO, "now booting...\n"); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - /* Halt if there was a built in self test failure. */ - report_bist_failure(bist); - setup_default_resource_map(); - setup_coherent_ht_domain(); - wait_all_core0_started(); - - printk(BIOS_INFO, "now booting... All core 0 started\n"); - -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - /* It is said that we should start core1 after all core0 launched. */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); -#endif - init_timer(); - ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ - - needs_reset = optimize_link_coherent_ht(); - printk(BIOS_DEBUG, "%02x", needs_reset); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - printk(BIOS_DEBUG, "%02x", needs_reset); - needs_reset |= k8t890_early_setup_ht(); - printk(BIOS_DEBUG, "%02x", needs_reset); - - vt8237_early_network_init(NULL); - vt8237_early_spi_init(); - - if (needs_reset) { - printk(BIOS_DEBUG, "ht reset -\n"); - soft_reset(); - printk(BIOS_DEBUG, "FAILED!\n"); - } - - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ - /* allow LDT STOP asserts */ - vt8237_sb_enable_fid_vid(); - - enable_fid_change(); - printk(BIOS_DEBUG, "after enable_fid_change\n"); - - init_fidvid_bsp(bsp_apicid); - - /* Stop the APs so we can start them later in init. */ - allow_all_aps_stop(bsp_apicid); - - /* It's the time to set ctrl now. */ - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -} |