1 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/early_init.c
new file mode 100644
index 0000000000..3a297f9e38
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/early_init.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states */
+	pnp_write_config(GLOBAL_DEV, 0x1a, 0x02);
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0x70);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
+	pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e);
+	pnp_write_config(GLOBAL_DEV, 0x22, 0xd7);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+
+	/* Power RAM in S3 */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}