diff options
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/p5gc-mx/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/asus/p5gc-mx/devicetree.cb | 13 | ||||
| -rw-r--r-- | src/mainboard/asus/p5gc-mx/romstage.c | 27 |
3 files changed, 25 insertions, 16 deletions
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index d29f98d59a..f0f0dd73f1 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 824beedb92..cefa7117fe 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -113,9 +113,20 @@ chip northbridge/intel/i945 device pnp 2e.6 off end # SPI device pnp 2e.7 on end # GPIO6 device pnp 2e.8 off end # WDTO# & PLED - device pnp 2e.9 on end # GPIO2-5 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xf0 = 0xf3 # BSEL straps to output + irq 0xf2 = 0x08 # INVERT GPIO33 + end + device pnp 2e.209 on # GPIO4 + irq 0xf5 = 0xf8 + end + device pnp 2e.309 on # GPIO5 + irq 0xe0 = 0xde + end device pnp 2e.a on # ACPI irq 0x70 = 0 + irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 end device pnp 2e.b on # HWM io 0x60 = 0x290 diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index efeaaec7e8..a29478c7d9 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -49,7 +49,7 @@ * BSEL1 is connected with GPIO33 with inversed logic * BSEL2 is connected with GPIO55 */ -static void setup_sio_gpio(u8 bsel) +static int setup_sio_gpio(u8 bsel) { int need_reset = 0; u8 reg, old_reg; @@ -83,13 +83,7 @@ static void setup_sio_gpio(u8 bsel) pnp_exit_ext_func_mode(GPIO_DEV); - if (need_reset) { - int i = 1000; - while (i--) - outb(i & 0xff, 0x80); - outb(0xe, 0xcf9); - halt(); - } + return need_reset; } static u8 msr_get_fsb(void) @@ -197,7 +191,6 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; - u8 m_bsel; u8 c_bsel = msr_get_fsb(); timestamp_init(get_initial_timestamp()); @@ -210,8 +203,6 @@ void mainboard_romstage_entry(unsigned long bist) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - setup_sio_gpio(c_bsel); - /* Set up the console */ console_init(); @@ -228,11 +219,19 @@ void mainboard_romstage_entry(unsigned long bist) */ i945_early_initialization(); - m_bsel = MCHBAR32(CLKCFG) & 7; - printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel); - s3resume = southbridge_detect_s3_resume(); + /* + * Result is that FSB is incorrect on s3 resume (fixed at 800MHz). + * Some CPU accept this others don't. + */ + if (!s3resume && setup_sio_gpio(c_bsel)) { + printk(BIOS_DEBUG, + "Needs reset to configure CPU BSEL straps\n"); + outb(0xe, 0xcf9); + halt(); + } + /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); |