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-rw-r--r--src/mainboard/asus/a8n_e/romstage.c10
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c7
-rw-r--r--src/mainboard/asus/m2n-e/romstage.c5
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c5
-rw-r--r--src/mainboard/asus/m2v/romstage.c12
-rw-r--r--src/mainboard/asus/m4a78-em/romstage.c7
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c7
-rw-r--r--src/mainboard/asus/m5a88-v/romstage.c3
8 files changed, 35 insertions, 21 deletions
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 29f425a225..c0fa6a52fd 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -21,8 +21,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* Used by it8712f_enable_serial(). */
+/* Used by ite_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#include <stdint.h>
#include <string.h>
@@ -33,7 +34,8 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -103,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- it8712f_24mhz_clkin();
- it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 4aa4b04e4a..487f0684a1 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -36,16 +36,19 @@
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
#include <string.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
/* TODO: remove .c includes */
#include <drivers/pc80/i8254.c>
#include <drivers/pc80/i8259.c>
-#include <superio/ite/it8712f/early_serial.c>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
it8712f_kill_watchdog();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_enable_3vsbsw();
console_init();
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index 6892b287bb..d12b77c5be 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -37,6 +37,7 @@
#include <spd.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -104,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24);
- it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
report_bist_failure(bist);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index ef0ce87726..0085bb42d5 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
- it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
console_init();
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 1ca145d704..acf8f9166e 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -46,6 +47,7 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define IT8712F_GPIO_BASE 0x0a20
@@ -163,15 +165,13 @@ static void m2v_it8712f_gpio_init(void)
* 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
* 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
*/
- it8712f_enter_conf();
giv = gpio_init_data;
while (giv->addr) {
printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
giv->addr, giv->val);
- it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
+ ite_reg_write(IT8712F_GPIO, giv->addr, giv->val);
giv++;
}
- it8712f_exit_conf();
printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
/*
@@ -225,8 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
- it8712f_24mhz_clkin();
- it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();
enable_rom_decode();
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 18c6f18151..93810d29b8 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 660ab0f4cb..b360636d1b 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 94a1e4e596..9fca93feca 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -41,6 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
+#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -100,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb800_clk_output_48Mhz();
- it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
printk(BIOS_DEBUG, "\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 20:46:19 +0000