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-rw-r--r--src/mainboard/asus/kcma-d8/romstage.c3
-rw-r--r--src/mainboard/asus/kfsn4-dre/romstage.c3
-rw-r--r--src/mainboard/asus/kgpe-d16/romstage.c5
-rw-r--r--src/mainboard/asus/m4a78-em/romstage.c3
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c3
-rw-r--r--src/mainboard/asus/m5a88-v/romstage.c3
6 files changed, 7 insertions, 13 deletions
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 4bcfeddf53..51d178fe88 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -51,7 +51,6 @@
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
inline int spd_read_byte(unsigned int device, unsigned int address)
{
@@ -355,7 +354,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
: "=r" (esp)
);
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
/* Limit the maximum HT speed to 2.6GHz to prevent lockups
* due to HT CPU <--> CPU wiring not being validated to 3.2GHz
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 817e6db22a..7b20243863 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -54,7 +54,6 @@
#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
int spd_read_byte(unsigned int device, unsigned int address)
{
@@ -184,7 +183,7 @@ void activate_spd_rom(const struct mem_controller *ctrl)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 85ad0b6f64..637ec42109 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -52,7 +52,6 @@
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
int spd_read_byte(unsigned int device, unsigned int address)
{
@@ -180,7 +179,7 @@ static const uint8_t spd_addr_fam10[] = {
void activate_spd_rom(const struct mem_controller *ctrl)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n");
@@ -467,7 +466,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
: "=r" (esp)
);
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
/* Limit the maximum HT speed to 2.6GHz to prevent lockups
* due to HT CPU <--> CPU wiring not being validated to 3.2GHz
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 072b758bef..c52b35b22f 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address)
@@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val;
msr_t msr;
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index c03115dc0b..b7af9e2cf5 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address)
@@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val;
msr_t msr;
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index ad05371367..1309d67d88 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -47,7 +47,6 @@
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address)
@@ -58,7 +57,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val;
msr_t msr;