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-rw-r--r--src/mainboard/bap/ode_e20XX/romstage.c4
-rw-r--r--src/mainboard/bap/ode_e21XX/romstage.c7
2 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 505de38d9e..c1b96f1273 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_ops.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
@@ -29,8 +30,7 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write(0xea, 1);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index 9729ffb400..a60e571367 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -38,8 +39,7 @@ static void romstage_main_template(void)
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
@@ -52,6 +52,5 @@ static void romstage_main_template(void)
void agesa_postcar(struct sysinfo *cb)
{
/* After AMD_INIT_ENV -> move to ramstage ? */
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
}