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-rw-r--r--src/mainboard/biostar/a68n_5200/romstage.c12
-rw-r--r--src/mainboard/biostar/am1ml/bootblock.c17
2 files changed, 12 insertions, 17 deletions
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c
index 5d210fa4be..09098f7d8b 100644
--- a/src/mainboard/biostar/a68n_5200/romstage.c
+++ b/src/mainboard/biostar/a68n_5200/romstage.c
@@ -21,12 +21,10 @@
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <amdblocks/acpimmio.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
-#define SB_MMIO 0xFED80000
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
-
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO)
@@ -36,14 +34,14 @@ static void sbxxx_enable_48mhzout(void)
/* most likely programming to 48MHz out signal */
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
u32 reg32;
- reg32 = SB_MMIO_MISC32(0x28);
+ reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
- SB_MMIO_MISC32(0x28) = reg32;
+ misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
- reg32 = SB_MMIO_MISC32(0x40);
+ reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
- SB_MMIO_MISC32(0x40) = reg32;
+ misc_write32(0x40, reg32);
}
void board_BeforeAgesa(struct sysinfo *cb)
diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c
index f198fe6809..771745e9bd 100644
--- a/src/mainboard/biostar/am1ml/bootblock.c
+++ b/src/mainboard/biostar/am1ml/bootblock.c
@@ -61,23 +61,20 @@ static void ite_gpio_conf(pnp_devfn_t dev)
void bootblock_mainboard_early_init(void)
{
- volatile u32 *addr32;
- u32 t32;
+ u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
- addr32 = (u32 *)0xfed80e28;
- t32 = *addr32;
- t32 &= 0xfff8ffff;
- *addr32 = t32;
+ reg32 = misc_read32(0x28);
+ reg32 &= 0xfff8ffff;
+ misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
- addr32 = (u32 *)0xfed80e40;
- t32 = *addr32;
- t32 &= 0xffffbffb;
- *addr32 = t32;
+ reg32 = misc_read32(0x40);
+ reg32 &= 0xffffbffb;
+ misc_write32(0x49, reg32);
/* Configure SIO as made under vendor BIOS */
ite_evc_conf(ENVC_DEV);