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-rw-r--r--src/mainboard/eaglelion/5bcm/Config.lb150
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diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb
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--- a/src/mainboard/eaglelion/5bcm/Config.lb
+++ /dev/null
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-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1
- device pci_domain 0 on
- device pci 0.0 on end
- chip southbridge/amd/cs5530
- device pci 12.0 on
- chip superio/nsc/pc97317
- device pnp 2e.0 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.1 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.2 on # RTC
- io 0x60 = 0x70
- irq 0x70 = 8
- end
- device pnp 2e.3 off # FDC
- end
- device pnp 2e.4 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.5 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.6 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.7 on # GPIO
- io 0x60 = 0xe0
- end
- device pnp 2e.8 on # Power Management
- io 0x60 = 0xe800
- end
- register "com1" = "{115200}"
- register "com2" = "{38400}"
- end
- device pci 12.1 off end # SMI
- device pci 12.2 on end # IDE
- device pci 12.3 off end # Audio
- device pci 12.4 off end # VGA
- end
- end
- end
-
- chip cpu/amd/model_gx1
- end
-
-end
-