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-rw-r--r--src/mainboard/emulation/qemu-x86/Config.lb123
-rw-r--r--src/mainboard/emulation/qemu-x86/Options.lb13
-rw-r--r--src/mainboard/emulation/qemu-x86/failover.c9
-rw-r--r--src/mainboard/emulation/qemu-x86/rom.c30
4 files changed, 117 insertions, 58 deletions
diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb
index 9af9df3c5c..cabcb2deeb 100644
--- a/src/mainboard/emulation/qemu-x86/Config.lb
+++ b/src/mainboard/emulation/qemu-x86/Config.lb
@@ -1,3 +1,5 @@
+## we don't use USE_DCACHE_RAM by default
+default USE_DCACHE_RAM=0
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
@@ -42,60 +44,77 @@ driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-mainboardinit cpu/x86/16bit/reset16.inc
-ldscript /cpu/x86/16bit/reset16.lds
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
+## ALL dependencies for USE_DCACHE_RAM go here.
+## That way, later, we can simply yank them if we wish.
+## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case.
+## we do not use failover yet in this case. This is a work in progress.
+if USE_DCACHE_RAM
+ ##
+ ##
+ mainboardinit arch/i386/init/entry.S
+ mainboardinit arch/i386/init/car.S
+ ldscript /arch/i386/init/ldscript.ld
+
+ ## The main code for the rom section is called rom.c
+ initobject rom.o
+else
+ ##
+ ## Romcc output
+ ##
+ makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+ makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+
+ ##
+ ## Build our 16 bit and 32 bit coreboot entry code
+ ##
+ mainboardinit cpu/x86/16bit/entry16.inc
+ mainboardinit cpu/x86/32bit/entry32.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ ldscript /cpu/x86/32bit/entry32.lds
+
+ ##
+ ## Build our reset vector (This is where coreboot is entered)
+ ##
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+
+ ### Should this be in the northbridge code?
+ mainboardinit arch/i386/lib/cpu_reset.inc
+
+ ##
+ ## Setup RAM
+ ##
+ mainboardinit cpu/x86/fpu/enable_fpu.inc
+ mainboardinit ./auto.inc
+
+ ## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
+ ##
+ ## Include an id string (For safe flashing)
+ ##
+ mainboardinit arch/i386/lib/id.inc
+ ldscript /arch/i386/lib/id.lds
+
+##
+## end of USE_DCACHE_RAM bits.
##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit ./auto.inc
+end
##
## Include the secondary Configuration files
diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb
index be18eb0b49..fdb69ffc47 100644
--- a/src/mainboard/emulation/qemu-x86/Options.lb
+++ b/src/mainboard/emulation/qemu-x86/Options.lb
@@ -41,7 +41,10 @@ uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
uses CONFIG_CONSOLE_SERIAL8250
uses USE_DCACHE_RAM
-
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
@@ -128,4 +131,12 @@ default CONFIG_ROM_PAYLOAD = 1
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
+##
+## known-good settings for qemu
+default DCACHE_RAM_BASE=0x8f000
+default DCACHE_RAM_SIZE=0x1000
+
+
+
+
end
diff --git a/src/mainboard/emulation/qemu-x86/failover.c b/src/mainboard/emulation/qemu-x86/failover.c
index 10bb2f48c1..07c6d1bc27 100644
--- a/src/mainboard/emulation/qemu-x86/failover.c
+++ b/src/mainboard/emulation/qemu-x86/failover.c
@@ -1,16 +1,14 @@
-#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
-#include "pc80/mc146818rtc_early.c"
-#include "cpu/x86/lapic/boot_cpu.c"
+/* no code inclusion allowed */
+//#include "pc80/mc146818rtc_early.c"
+//#include "cpu/x86/lapic/boot_cpu.c"
static void main(void)
{
- /* for now, just always assume failure */
-
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
@@ -27,3 +25,4 @@ static void main(void)
}
#endif
}
+
diff --git a/src/mainboard/emulation/qemu-x86/rom.c b/src/mainboard/emulation/qemu-x86/rom.c
new file mode 100644
index 0000000000..65c2644599
--- /dev/null
+++ b/src/mainboard/emulation/qemu-x86/rom.c
@@ -0,0 +1,30 @@
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <cbfs.h>
+
+/*
+ */
+void udelay(int usecs)
+{
+ int i;
+ for(i = 0; i < usecs; i++)
+ outb(i&0xff, 0x80);
+}
+
+void main(void)
+{
+ int i;
+ void uart_init(void);
+ void (*start_address)();
+ outb(5, 0x80);
+
+ uart_init();
+ start_address = cbfs_load_stage("fallback/coreboot_ram");
+ start_address();
+
+}