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-rw-r--r--src/mainboard/foxconn/g41s-k/Makefile.inc3
-rw-r--r--src/mainboard/foxconn/g41s-k/early_init.c (renamed from src/mainboard/foxconn/g41s-k/romstage.c)3
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc
index ca8de4d597..161c623eaa 100644
--- a/src/mainboard/foxconn/g41s-k/Makefile.inc
+++ b/src/mainboard/foxconn/g41s-k/Makefile.inc
@@ -1,6 +1,9 @@
ramstage-y += cstates.c
romstage-y += gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c
+
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/early_init.c
index b4bd77d78b..454b1ea0b0 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/early_init.c
@@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/ite/common/ite.h>
@@ -24,7 +25,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
-void mb_lpc_setup(void)
+void bootblock_mainboard_early_init(void)
{
/* Set up GPIOs on Super I/O. */
ite_reg_write(GPIO_DEV, 0x25, 0x01);