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-rw-r--r--src/mainboard/getac/p470/romstage.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index a081a8a8a2..0f746e1b75 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -26,6 +26,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
+#include <arch/acpi.h>
#include <cbmem.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
@@ -304,17 +305,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+ if (acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ } else {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ }
}
/* Enable SPD ROMs and DDR-II DRAM */