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-rw-r--r--src/mainboard/gigabyte/ga-6bxe/Kconfig53
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/chip.h22
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/devicetree.cb57
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/irq_tables.c53
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/mainboard.c26
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/romstage.c70
6 files changed, 281 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-6bxe/Kconfig b/src/mainboard/gigabyte/ga-6bxe/Kconfig
new file mode 100644
index 0000000000..01106f285a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config BOARD_GIGABYTE_GA_6BXE
+ bool "GA-6BXE"
+ select ARCH_X86
+ select CPU_INTEL_SLOT_1
+ select NORTHBRIDGE_INTEL_I440BX
+ select SOUTHBRIDGE_INTEL_I82371EB
+ select SUPERIO_ITE_IT8671F
+ select ROMCC
+ select HAVE_PIRQ_TABLE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_256
+ select SDRAMPWR_4DIMM
+
+config MAINBOARD_DIR
+ string
+ default gigabyte/ga-6bxe
+ depends on BOARD_GIGABYTE_GA_6BXE
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GA-6BXE"
+ depends on BOARD_GIGABYTE_GA_6BXE
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_GIGABYTE_GA_6BXE
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+ depends on BOARD_GIGABYTE_GA_6BXE
+
diff --git a/src/mainboard/gigabyte/ga-6bxe/chip.h b/src/mainboard/gigabyte/ga-6bxe/chip.h
new file mode 100644
index 0000000000..8e3af56a19
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ga-6bxe/devicetree.cb b/src/mainboard/gigabyte/ga-6bxe/devicetree.cb
new file mode 100644
index 0000000000..f84c7b38d8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/devicetree.cb
@@ -0,0 +1,57 @@
+chip northbridge/intel/i440bx # Northbridge
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_1 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/ite/it8671f # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.2 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.4 on # APC
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 3f0.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 3f0.7 on # GPIO
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga-6bxe/irq_tables.c b/src/mainboard/gigabyte/ga-6bxe/irq_tables.c
new file mode 100644
index 0000000000..b46dade6e2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/irq_tables.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x07 << 3) | 0x0, /* Interrupt router dev */
+ 0xc00, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x7000, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xb4, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x08 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0},
+ {0x00, (0x09 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x5, 0x0},
+ {0x00, (0x07 << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/gigabyte/ga-6bxe/mainboard.c b/src/mainboard/gigabyte/ga-6bxe/mainboard.c
new file mode 100644
index 0000000000..2d047946f8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/mainboard.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE GA-6BXE Mainboard")
+};
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
new file mode 100644
index 0000000000..35ecb9688b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "superio/ite/it8671f/it8671f_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i440bx/raminit.c"
+#include "northbridge/intel/i440bx/debug.c"
+
+static void main(unsigned long bist)
+{
+ if (bist == 0)
+ early_mtrr_init();
+
+ /* it8671f_48mhz_clkin(); */
+ it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+ report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
+ enable_smbus();
+ /* dump_spd_registers(); */
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
+ /* ram_check(0, 640 * 1024); */
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 19:39:05 +0000