summaryrefslogtreecommitdiff
path: root/src/mainboard/gigabyte/m57sli/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/gigabyte/m57sli/romstage.c')
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index d606040d2c..7665c7b622 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -35,6 +35,7 @@
#include <console/console.h>
#include <usbdebug.h>
+#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@@ -131,11 +132,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
- (0xa<<3)|0, (0xa<<3)|2, 0, 0,
- (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
// Node 1
- (0xa<<3)|4, (0xa<<3)|6, 0, 0,
- (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE