summaryrefslogtreecommitdiff
path: root/src/mainboard/gigabyte/m57sli
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/gigabyte/m57sli')
-rw-r--r--src/mainboard/gigabyte/m57sli/Kconfig74
-rw-r--r--src/mainboard/gigabyte/m57sli/Kconfig.name2
-rw-r--r--src/mainboard/gigabyte/m57sli/Makefile.inc16
-rw-r--r--src/mainboard/gigabyte/m57sli/acpi_tables.c82
-rw-r--r--src/mainboard/gigabyte/m57sli/board_info.txt7
-rw-r--r--src/mainboard/gigabyte/m57sli/cmos.default9
-rw-r--r--src/mainboard/gigabyte/m57sli/cmos.layout69
-rw-r--r--src/mainboard/gigabyte/m57sli/devicetree.cb154
-rw-r--r--src/mainboard/gigabyte/m57sli/dsdt.asl300
-rw-r--r--src/mainboard/gigabyte/m57sli/fanctl.c81
-rw-r--r--src/mainboard/gigabyte/m57sli/get_bus_conf.c120
-rw-r--r--src/mainboard/gigabyte/m57sli/hda_verb.c7
-rw-r--r--src/mainboard/gigabyte/m57sli/irq_tables.c111
-rw-r--r--src/mainboard/gigabyte/m57sli/mptable.c122
-rw-r--r--src/mainboard/gigabyte/m57sli/resourcemap.c278
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c210
16 files changed, 0 insertions, 1642 deletions
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
deleted file mode 100644
index 28473776bb..0000000000
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-if BOARD_GIGABYTE_M57SLI
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_ITE_IT8716F
- select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default gigabyte/m57sli
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "GA-M57SLI-S4"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config MCP55_PCI_E_X_0
- int
- default 0
-
-endif # BOARD_GIGABYTE_M57SLI
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig.name b/src/mainboard/gigabyte/m57sli/Kconfig.name
deleted file mode 100644
index 32a5470fb8..0000000000
--- a/src/mainboard/gigabyte/m57sli/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GIGABYTE_M57SLI
- bool "GA-M57SLI-S4"
diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc
deleted file mode 100644
index c18f22441a..0000000000
--- a/src/mainboard/gigabyte/m57sli/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c
diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c
deleted file mode 100644
index 72b82f5f4d..0000000000
--- a/src/mainboard/gigabyte/m57sli/acpi_tables.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <device/pci.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
- extern unsigned char bus_mcp55[8];
- extern unsigned apicid_mcp55;
-
- unsigned sbdn;
- struct resource *res;
- struct device *dev;
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- apicid_mcp55, res->base, 0);
- }
- }
-
- /* Write NB IOAPIC. */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- apicid_mcp55++, res->base, gsi_base);
- }
- }
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/gigabyte/m57sli/board_info.txt b/src/mainboard/gigabyte/m57sli/board_info.txt
deleted file mode 100644
index 33c36557c2..0000000000
--- a/src/mainboard/gigabyte/m57sli/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2287#ov
-ROM socketed: n
-Flashrom support: y
-Vendor cooperation score: 3
-Vendor cooperation page: Gigabyte m57sli Vendor Cooperation Score
-Release year: 2006
diff --git a/src/mainboard/gigabyte/m57sli/cmos.default b/src/mainboard/gigabyte/m57sli/cmos.default
deleted file mode 100644
index 62068cf4a7..0000000000
--- a/src/mainboard/gigabyte/m57sli/cmos.default
+++ /dev/null
@@ -1,9 +0,0 @@
-debug_level = Spew
-multi_core = Enable
-slow_cpu = off
-max_mem_clock = 200Mhz
-ECC_memory = Enable
-hw_scrubber = Enable
-interleave_chip_selects = Enable
-power_on_after_fail = Disable
-boot_option = Fallback
diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/gigabyte/m57sli/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb
deleted file mode 100644
index efbf76e896..0000000000
--- a/src/mainboard/gigabyte/m57sli/devicetree.cb
+++ /dev/null
@@ -1,154 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_AM2 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
-end
-device domain 0 on # PCI domain
- subsystemid 0x1022 0x2b80 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8716f # Super I/O
- device pnp 2e.0 on # Floppy and any LDN
- # Watchdog from CLKIN (24 MHz)
- irq 0x23 = 0x11
- # Serial Flash (SPI only)
- # 0x24 = 0x1a
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Embedded controller
- io 0x60 = 0x290
- io 0x62 = 0x230
- irq 0x70 = 9
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 on # GPIO, SPI flash
- # Pin 84 is not GP10
- irq 0x25 = 0x0
- # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
- irq 0x26 = 0x43
- # Pin 13 is GP35
- irq 0x27 = 0x20
- # Pin 70 is not GP46
- # irq 0x28 = 0x0
- # Pin 6,3,128,127,126 is GP63,64,65,66,67
- irq 0x29 = 0x81
- # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23),
- # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22),
- # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal
- # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal
- # voltage divider for VCC5V
- # irq 0x2c = 0x1f
- # Simple I/O base
- io 0x62 = 0x800
- # Serial Flash I/O (SPI only)
- io 0x64 = 0x820
- # Watchdog force timeout (parallel flash only)
- # irq 0x71 = 0x1
- # No WDT interrupt
- irq 0x72 = 0x0
- # GPIO pin set 1 disable internal pullup
- irq 0xb8 = 0x0
- # GPIO pin set 5 enable internal pullup
- irq 0xbc = 0x01
- # SIO pin set 1 alternate function
- # irq 0xc0 = 0x0
- # SIO pin set 2 mixed function
- irq 0xc1 = 0x43
- # SIO pin set 3 mixed function
- irq 0xc2 = 0x20
- # SIO pin set 4 alternate function
- # irq 0xc3 = 0x0
- # SIO pin set 1 input mode
- # irq 0xc8 = 0x0
- # SIO pin set 2 input mode
- irq 0xc9 = 0x0
- # SIO pin set 4 input mode
- # irq 0xcb = 0x0
- # Generate SMI# on EC IRQ
- # irq 0xf0 = 0x10
- # SMI# level trigger
- # irq 0xf1 = 0x40
- # HWMON alert beep pin location
- irq 0xf6 = 0x28
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 off # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # Consumer IR
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 on end # AUDIO
- device pci 8.0 on end # NIC
- device pci 9.0 off end # N/A
- device pci a.0 on end # PCI E 5
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl
deleted file mode 100644
index c53f36a47e..0000000000
--- a/src/mainboard/gigabyte/m57sli/dsdt.asl
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
- })
-
- Device (PEBF) /* PCI-E Bridge F */
- {
- Name (_ADR, 0x000F0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x07)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (PEBE) /* PCI-E Bridge E */
- {
- Name (_ADR, 0x000E0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (PEBD) /* PCI-E Bridge D */
- {
- Name (_ADR, 0x000D0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 },
- })
- }
-
- Device (PEBC) /* PCI-E Bridge C */
- {
- Name (_ADR, 0x000C0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
- })
- }
-
- Device (PEBB) /* PCI-E Bridge B */
- {
- Name (_ADR, 0x000B0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (PEBA) /* PCI-E Bridge A */
- {
- Name (_ADR, 0x000A0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (PCID) /* PCI Device */
- {
- Name (_ADR, 0x00060000)
- Name (_UID, 0x00)
- Name (_BBN, 0x01)
- Name (_PRT, Package () {
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
- Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
- })
- }
- }
-
- Device (ISA) {
- Name (_ADR, 0x000010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP0, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP0)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP1, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {12}
- })
- Return (TMP1)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
- IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- /* Parallel Port */
- Device (LPT1)
- {
- Name (_HID, EisaId ("PNP0400"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
- IRQNoFlags () {7}
- })
- Return (BUF1)
- }
- }
- /* Parallel Port ECP */
- Device (ECP1)
- {
- Name (_HID, EisaId ("PNP0401"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x04)
- IO (Decode16, 0x0778, 0x0778, 0x01, 0x04)
- IRQNoFlags() {7}
- DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3}
- })
- Return (BUF1)
- }
- }
- }
- }
-}
diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c
deleted file mode 100644
index cc0cdcac23..0000000000
--- a/src/mainboard/gigabyte/m57sli/fanctl.c
+++ /dev/null
@@ -1,81 +0,0 @@
-#include <arch/io.h>
-#include <stdlib.h>
-#include <superio/ite/it8716f/it8716f.h>
-
-static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static const struct {
- uint8_t index, value;
-} sequence[]= {
- /* Make sure we can monitor, and enable SMI# interrupt output */
- { 0x00, 0x13},
- /* Disable fan interrupt status bits for SMI# */
- { 0x04, 0x37},
- /* Disable VIN interrupt status bits for SMI# */
- { 0x05, 0xff},
- /* Disable fan interrupt status bits for IRQ */
- { 0x07, 0x37},
- /* Disable VIN interrupt status bits for IRQ */
- { 0x08, 0xff},
- /* Disable external sensor interrupt */
- { 0x09, 0x87},
- /* Enable 16 bit counter divisors */
- { 0x0c, 0x07},
- /* Set FAN_CTL control register (0x14) polarity to high, and
- activate fans 1, 2 and 3. */
- { 0x14, 0xd7},
- /* set the correct sensor types 1,2 thermistor; 3 diode */
- { 0x51, 0x1c},
- /* set the 'zero' voltage for diode type sensor 3 */
- { 0x5c, 0x80},
-// { 0x56, 0xe5},
-// { 0x57, 0xe5},
- { 0x59, 0xec},
- { 0x5c, 0x00},
- /* fan1 (controlled by temp3) control parameters */
- /* fan off limit */
- { 0x60, 0xff},
- /* fan start limit */
- { 0x61, 0x14},
- /* ???? */
-// { 0x62, 0x00},
- /* start PWM */
- { 0x63, 0x27},
- /* smooth and slope PWM */
- { 0x64, 0x90},
- /* direct-down and interval */
- { 0x65, 0x03},
- /* temperature limit of fan stop for fan3 (automatic) */
- { 0x70, 0xff},
- /* temperature limit of fan start for fan3 (automatic) */
- { 0x71, 0x14},
- /* Set PWM start & slope for fan3 */
- { 0x73, 0x20},
- /* Initialize PWM automatic mode slope values for fan3 */
- { 0x74, 0x90},
- /* set smartguardian temperature interval for fan3 */
- { 0x75, 0x03},
- /* fan1 auto controlled by temp3 */
- { 0x15, 0x82},
- /* fan2 auto controlled by temp3 */
- { 0x16, 0x82},
- /* fan3 auto controlled by temp3 */
- { 0x17, 0x82},
- /* all fans enable, fan1 ctl smart */
- { 0x13, 0x77}
-};
-
-/*
- * Called from superio.c
- */
-void init_ec(uint16_t base)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(sequence); i++) {
- write_index(base, sequence[i].index, sequence[i].value);
- }
-}
diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
deleted file mode 100644
index 5ef79627b4..0000000000
--- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_mcp55[8]; //1
-unsigned apicid_mcp55;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 8; i++) {
- bus_mcp55[i] = 0;
- }
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x06);
-
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev =
- dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev) {
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-
-}
diff --git a/src/mainboard/gigabyte/m57sli/hda_verb.c b/src/mainboard/gigabyte/m57sli/hda_verb.c
deleted file mode 100644
index 072a306131..0000000000
--- a/src/mainboard/gigabyte/m57sli/hda_verb.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c
deleted file mode 100644
index 4d42d7495c..0000000000
--- a/src/mainboard/gigabyte/m57sli/irq_tables.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_mcp55[8]; //1
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
deleted file mode 100644
index e9ffe52b73..0000000000
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_mcp55[8]; //1
-
-extern unsigned apicid_mcp55;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, j, k, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
- /* set up the interrupt registers of mcp55 */
- pci_write_config32(dev, 0x7c, 0xc643c643);
- pci_write_config32(dev, 0x80, 0x8da01009);
- pci_write_config32(dev, 0x84, 0x200018d2);
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
-/* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
- bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
-
- PCI_INT(0,sbdn+1,1, 10); /* SMBus */
- PCI_INT(0,sbdn+2,0, 22); /* USB */
- PCI_INT(0,sbdn+2,1, 23); /* USB */
- PCI_INT(0,sbdn+4,0, 21); /* IDE */
- PCI_INT(0,sbdn+5,0, 20); /* SATA */
- PCI_INT(0,sbdn+5,1, 21); /* SATA */
- PCI_INT(0,sbdn+5,2, 22); /* SATA */
- PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
- PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
-
- /* The PCIe slots, each on its own bus */
- k = 1;
- for(i = 0; i < 4; i++){
- for(j = 7; j > 1; j--){
- if(k > 3) k = 0;
- PCI_INT(j,0,i, 16+k);
- k++;
- }
- k--;
- }
-
- /* On bus 1: the PCI bus slots...
- * physical PCI slots are j = 7,8
- * FireWire is j = 10
- */
- k = 2;
- for(i = 0; i < 4; i++){
- for(j = 6; j < 11; j++){
- if(k > 3) k = 0;
- PCI_INT(1,j,i, 16+k);
- k++;
- }
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
deleted file mode 100644
index 35c54c8344..0000000000
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
deleted file mode 100644
index 3261c5dcb8..0000000000
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8716f/it8716f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-#if 0
- uint8_t tmp = 0;
- pnp_enter_ext_func_mode(SERIAL_DEV);
- /* The following line will set CLKIN to 24 MHz, external */
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
- tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
- /* Is serial flash enabled? Then enable writing to serial flash. */
- if (tmp & 0x0e) {
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
- pnp_set_logical_device(GPIO_DEV);
- /* Set Serial Flash interface to 0x0820 */
- pnp_write_config(GPIO_DEV, 0x64, 0x08);
- pnp_write_config(GPIO_DEV, 0x65, 0x20);
- }
- it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pnp_exit_ext_func_mode(SERIAL_DEV);
-#endif
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- setup_mb_resource_map();
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); // Need to use TMICT to synchronize FID/VID
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 04:52:45 +0000