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-rw-r--r--src/mainboard/gigabyte/ga-6bxc/Kconfig1
-rw-r--r--src/mainboard/gigabyte/ga-6bxc/romstage.c13
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/Kconfig1
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/romstage.c12
4 files changed, 8 insertions, 19 deletions
diff --git a/src/mainboard/gigabyte/ga-6bxc/Kconfig b/src/mainboard/gigabyte/ga-6bxc/Kconfig
index f89c44088f..04b73d1876 100644
--- a/src/mainboard/gigabyte/ga-6bxc/Kconfig
+++ b/src/mainboard/gigabyte/ga-6bxc/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c
index 1f58a0031b..040e762d24 100644
--- a/src/mainboard/gigabyte/ga-6bxc/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c
@@ -26,16 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
@@ -47,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +58,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/gigabyte/ga-6bxe/Kconfig b/src/mainboard/gigabyte/ga-6bxe/Kconfig
index 34a3281d78..e49dc1d4a7 100644
--- a/src/mainboard/gigabyte/ga-6bxe/Kconfig
+++ b/src/mainboard/gigabyte/ga-6bxe/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index f9b5135402..aafd39453c 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -26,16 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+static void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
@@ -47,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
it8671f_48mhz_clkin();
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -62,9 +59,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}